AD9161BBCZ datasheet(79/144 Pages) AD

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Data Sheet

AD9161/AD9162

Rev. D | Page 79 of 144

The improvement in performance from making these

adjustments depends on the accuracy of the balance of the clock

input balun and varies from unit to unit. Thus, if a high level of

image rejection is required, it is likely that a per unit calibration

is necessary. Performing this calibration can yield significant

improvements, as much as 20 dB additional rejection of the

image due to imbalance. Figure 187 shows the results of tuning

clock phase, duty cycle (left at default in this case), and cross

control. The improvement to performance, particularly at

higher frequencies, can be as much as 20 dB.

PHASE 0,

CROSS 6

–20

–30

–40

–50

–60

–70

–80

–90

1000

2000

3000

4000

5000

6000

PHASE 28,

CROSS 10

fOUT (MHz)

Figure 187. Performance Improvement from Tuning the Clock Input

SHUFFLE MODE

The spurious performance of the AD9161/AD9162 can be

improved with a feature called shuffle mode. Shuffle mode uses

proprietary technology to spread the energy of spurious signals

across the DAC output as random noise. Shuffle mode is

enabled by programming Register 0x151, Bit 2 = 0b1. Because

shuffle is implemented with the MSBs, it is more effective when

the DAC is operated with a small amount of digital backoff.

The amount of noise rise caused by shuffle mode is directly

related to the power in the affected spurious signals. Because

the AD9161/AD9162 have good spurious performance without

shuffle active, the penalty of shuffle mode to the noise spectral

density is typically about 1 dB to 3 dB. Shuffle mode reduces

spurious performance related to clock and foldback spurs, but

does not affect real harmonics of the DAC output. Examples of

the effects of shuffle mode are given in the Typical Performance

Characteristics section (see Figure 18, Figure 19, Figure 33,

Figure 34, Figure 100, Figure 101, Figure 115, Figure 116, and

Figure 117).

DLL

The CLK± input goes to a high frequency DLL to ensure robust

locking of the DAC sample clock to the input clock. The DLL is

configured and enabled as part of the recommended start-up

sequence. The DLL control registers are located at Register 0x090

through Register 0x09B. The DLL settings are determined during

product characterization and are given in the recommended

start-up sequence (see the Start-Up Sequence section). It is not

normally necessary to change these values, nor is the product

characterization data valid on any settings other than the recom-

mended ones.

VOLTAGE REFERENCE

The AD9161/AD9162 output current is set by a combination of

digital control bits and the ISET reference current, as shown in

Figure 188.

CURRENT

SCALING

ANA_FULL_SCALE_CURRENT [9:0]

AD9161/AD9162

DAC

IOUTFS

9.6kΩ

1µF

VREF

ISET

VSS

ISET

VBG

1.2V

–

VNEG_N1P2

Figure 188. Voltage Reference Circuit

The reference current is obtained by forcing the band gap

voltage across an external 9.6 kΩ resistor from ISET (Ball A15

on the 8 mm × 8 mm package and Ball A12 on the 11 mm ×

11 mm package) to VNEG_N1P2. The 1.2 V nominal band gap

voltage (VREF) generates a 125 µA reference current, ISET, in

the 9.6 kΩ resistor, RSET. The maximum full-scale current

setting is related to the external resistor by the following

equation:

IOUTFS = 1.2 V/RSET (kΩ) × 320 (mA)

Note the following constraints when configuring the voltage

reference circuit:

•

Both the 9.6 kΩ resistor and 1 µF bypass capacitor are

required for proper operation.

•

Adjusting the DAC output full-scale current, IOUTFS, from

its default setting of 40 mA must be performed digitally.

•

The AD9161/AD9162 are not multiplying DACs.

Modulation of the reference current, ISET, with an ac

signal is not supported.

•

The band gap voltage appearing at the VREF pin must be

buffered for use with an external circuitry because it has a

high output impedance.

•

An external reference can be used to overdrive the internal

reference by connecting it to the VREF pin.

The IOUTFS value can be adjusted digitally over an 8 mA to

40 mA range by the ANA_FULL_SCALE_CURRENT[9:0] bits

(Register 0x042, Bits[7:0] and Register 0x041, Bits[1:0]). The

following equation relates IOUTFS to the ANA_FULL_SCALE_

CURRENT[9:0] bits, which can be set from 0 to 1023.

IOUTFS = 32 mA × (ANA_FULL_SCALE_CURRENT[9:0]/1023) +

8 mA

Note that the default value of 0x3FF generates 40 mA full scale,

and this value is used for most of the characterization presented

in this data sheet, unless noted otherwise.

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