AD9161BBCZ datasheet(91/144 Pages) AD

91 / 144 page

Data Sheet

AD9161/AD9162

Rev. D | Page 91 of 144

Table 46. Register Details

Hex.

Addr. Name

Bits Bit Name

Settings

Description

Reset

Access

0x000 SPI_INTFCONFA

SOFTRESET_M

Soft reset (mirror). Set this to

mirror Bit 0.

0x0

LSBFIRST_M

LSB first (mirror). Set this to

mirror Bit 1.

0x0

ADDRINC_M

Addr increment (mirror). Set

this to mirror Bit 2.

0x0

SDOACTIVE_M

SDO active (mirror). Set this to

mirror Bit 3.

0x0

SDOACTIVE

SDO active. Enables 4-wire SPI

bus mode.

0x0

R/W

ADDRINC

Address increment. When set,

causes incrementing streaming

addresses; otherwise,

descending addresses are

generated.

0x0

R/W

1 Streaming addresses are

incremented.

0 Streaming addresses are

decremented.

LSBFIRST

LSB first. When set, causes input

and output data to be oriented

as LSB first. If this bit is clear,

data is oriented as MSB first.

0x0

R/W

1 Shift LSB in first.

0 Shift MSB in first.

SOFTRESET

Soft reset. This bit automatically

clears to 0 after performing a

reset operation. Setting this bit

initiates a reset. This bit is

autoclearing after the soft reset

is complete.

0x0

R/W

1 Pulse the soft reset line.

0 Reset the soft reset line.

0x001 SPI_INTFCONFB

SINGLEINS

Single instruction.

0x0

R/W

1 Perform single transfers.

0 Perform multiple transfers.

CSSTALL

CS stalling.

0x0

R/W

0 Disable CS stalling.

1 Enable CS stalling.

[5:3] RESERVED

Reserved.

0x0

R/W

SOFTRESET1

Soft Reset 1. This bit

automatically clears to 0 after

performing a reset operation.

0x0

R/W

1 Pulse the Soft Reset 1 line.

0 Pulse the Soft Reset 1 line.

SOFTRESET0

Soft Reset 0. This bit

automatically clears to 0 after

performing a reset operation.

0x0

R/W

1 Pulse the Soft Reset 0 line.

0 Pulse the Soft Reset 0 line.

RESERVED

Reserved.

0x0

0x003 SPI_CHIPTYPE

[7:0] CHIP_TYPE

Chip type.

0x0

0x004 SPI_PRODIDL

[7:0] PROD_ID[7:0]

Product ID.

0x0

0x005 SPI_PRODIDH

[7:0] PROD_ID[15:8]

Product ID.

0x0

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