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PC8374L датащи(PDF) 88 Page - National Semiconductor (TI) |
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PC8374L датащи(HTML) 88 Page - National Semiconductor (TI) |
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88 / 239 page ![]() 4.0 System Wake-Up Control (SWC) (Continued) www.national.com 88 Revision1.1 The LEDMOD field controls the operation mode of GRN_LED and YLW_LED pins in each system power state (see Table 38 on page 93). The system power state is identified either by the status of the VDD3 power supply or by the current system sleep state: • ‘00’ – The behavior of the GRN_LED and YLW_LED pins is controlled solely by software by the setting of the GRNBLNK and YLWBLNK fields. • ‘01’ – The behavior of the GRN_LED and YLW_LED pins is controlled by the status of the V DD3 supply and by software. In the Power Off state (VDD3 off), the GRN_LED behaves according to the setting of the GRNBLNK field, but the YLW_LED blinks at a 1 Hz rate with a 50% duty cycle; In the Power On state (VDD3 on), each LED behaves according to the setting of its xxxBLNK field. • ‘10’ – The behavior of the GRN_LED and YLW_LED pins is controlled by the S5 sleep state and by software. In S5 sleep state, both LEDs are off; In S3 - S0 sleep states, each LED behaves according to the setting of its xxxBLNK field. • ‘11’ – The behavior of the GRN_LED and YLW_LED pins is controlled by the status of the V DD3 supply and by software. In the Power Off state (VDD3 off), both LEDs are off; In Power On state (VDD3 on), each LED behaves according to the setting of its xxxBLNK field. The status of the VDD3 power supply is detected by internal circuits, which identify the Power Off and Power On states (see Section 2.1.2 on page 32). The current system sleep state is decoded from the levels of the SLP_S3 and SLP_S5 pins (see Section 4.2.3 on page 86). Only sleep state S5 is relevant. The GRNBLNK and YLWBLNK fields in LEDBLNK register (at offset 03h; see Section 4.3.6 on page 95) control the On/Off state or the blinking rate of the GRN_LED and YLW_LED pins, respectively. For each LED pin, a different blink rate can be selected. Different blink rates can also be selected for the dual-color LED mode (LEDCFG = 0). Special LED Control Special LED control is the default LED control option. In the Special LED control option, configuration “b” or “c” in Figure 14 can be used. In this option, LED operation is controlled by the bits of XLEDCTL register (at offset 02h; see Section 4.3.5 on page 94) and by the SLP_S3, SLP_S5 and PWRGD_PS pins. When the system is in sleep state S5 (SLP_S5 = 0), both LEDs are off. When the system is in sleep state S3 (SLP_S3 = 0) or S1 (SLP_S1 bit is set), the green LED blinks and the yellow LED is off. The green and yellow LED operation is reversed when the system is in the working state (S0) and the Main power supply is not functional (PWRGD_PS = 0). When the system is in working state (S0) and the Main power supply is within the spec- ified limits, SW_CTL bit selects the active LED (On) of the two, and the other LED is turned off. The blinking rate of the LEDs is 1 Hz with a duty cycle of 50%. Table 39 on page 94 shows the states of the GRN_LED and YLW_LED pins. The LEDs are connected according to config- uration “b” (see Figure 14 on page 87); therefore, a LED is On when the pin is floated; it is Off when the pin is at low level (0). Table 35. LEDs “On” Polarity as a Function of LEDCFG and LEDPOL LEDCFG LEDPOL GRN_LED YLW_LED Connection (See Figure 14) 0 0 TRI-STATE 0 “c”, Green anode to GRN_LED pin 0 1 0 TRI-STATE “c”, Yellow anode to GRN_LED pin 1 0 TRI-STATE TRI-STATE “b” 1100 “a” Winbond Electronics Corp. Advanced PC Product Center |
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