PC8374L datasheet(76/239 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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Revision1.1

Table 31. Reset Values for PUPCTL and PDNCTL Bits

R/W or

EVDBNC (Event Debounce Enable). Enables the debounce circuit in the event input path of the

selected GPIO pin. The event is detected after a predetermined debouncing period (see Section 6.3 on

page 113).

0: Disabled (default)

1: Enabled

Reserved for Port 1, Pin 5.

R/W or

EVPOL (Event Polarity). Deﬁnes the polarity of the wake-up signal that issues an event from the

selected GPIO pin (see Section 6.3 on page 113).

0: Falling edge or low level input (default)

1: Rising edge or high level input

Reserved for Port 1, Pin 5.

R/W or

EVTYPE (Event Type). Deﬁnes the type of the wake-up signal that issues an event from the selected

GPIO pin (see Section 6.3 on page 113).

0: Edge input (default)

1: Level input

Reserved for Port 1, Pin 5.

R/W1S LOCKCFP (Lock Configuration of Pin). When set to 1, locks the GPIO pin conﬁguration and data

(also see Section 6.4 on page 115) by disabling writing to itself, to GPCFG1 register bits PDNCTL,

PUPCTL, OUTTYPE and OUTENA, to all of the bits of GPCFG2 register and to the corresponding bit

in GPDO and GPDIO registers. Once set, this bit can be cleared by Hardware reset.

0: R/W bits are enabled for write (default)

1: All bits are RO

R/W or

PUPCTL (Pull-Up Control). Controls the internal pull-up resistor of the selected GPIO pin (see

Section 6.2 on page 111).

0: Disabled (for default value, see Table 31)

1: Enabled (for default value, see Table 31)

Undefined results when both the PDNCTL bit and the PUPCTL bit are set to 1.

R/W or

OUTTYPE (Output Type). Controls the output buffer type of the selected GPIO pin (see Section 6.2 on

page 111).

0: Open-drain (default)

1: Push-pull

R/W or

OUTENA (Output Enable). Controls the output buffer of the selected GPIO pin (see Section 6.2 on

page 111).

0: TRI-STATE (default)

1: Output buffer enabled

GP(I)O(E)nn

01-06

11-13

15-16

PUPCTL

010

PDNCTL

No Pull-Down

Bit

Type

Description

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