PC8374L datasheet(77/239 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

Revision 1.1

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3.14.5 GPIO Event Routing Register (GPEVR)

This register reflects, for both read and write, the register currently selected by the GPIO Pin Select register. It enables the

routing of the GPIO event (see Section 6.3.2 on page 114) to an IRQ and/or SMI signal. It is implemented for Ports 0 to 1,

which have wake-up event detection capability. GPEVR is reset to 00h.

Power Well: VSB3

Location:

Index F2h

Type:

R/W or RO

3.14.6 GPIO Pin Configuration Register 2 (GPCFG2)

This register reflects, for both read and write, the register currently selected by the GPIO Pin Select register. It controls the

connection of the GPIO pin to a VDD-powered load.

Power Well: VSB3

Location:

Index F3h

Type:

R/W or RO

Table 32. Reset Values for VDDLOAD Bit

Bit

76543210

Name

Reserved

EV2SMI

EV2IRQ

Reset

00000000

Bit

Description

7-2

Reserved.

EV2SMI (Event to SMI Routing). Controls the routing of the event from the selected GPIO pin to SMI (see

Section 6.3.2 on page 114).

0: Disabled (default)

1: Enabled

EV2IRQ (Event to IRQ Routing). Controls the routing of the event from the selected GPIO pin to IRQ (see

Section 6.3.2 on page 114).

0: Disabled (default)

1: Enabled

Bit

765

210

Name

Reserved

VDDLOAD

Reserved

Reset

see Table 32

Bit

Description

7-5

Reserved.

VDDLOAD (VDD3-Powered Load). Indicates that the selected GPIO pin is connected to a device powered by

VDD3. When this bit is 1, the input and output buffers (including the internal pull-up/pull-down) of the selected

GPIO pin are disabled whenever VDD3 power to the PC8374L device falls below a certain value (see

Section 10.1.5 on page 213).

0: GPIO pin connected to a VSB3-powered load (default): The configuration and data of the GPIO pin are reset

by VSB3 Power-Up reset (see Section 2.2 on page 34).

1: GPIO pin connected to a VDD3-powered load: The configuration (excepting the VDDLOAD bit) and data of the

GPIO pin are reset by VDD Power-Up reset, Hardware reset or Software reset (see Section 2.2 on page 34).

3-0

Reserved.

GP(I)O(E)nn

01-07

11-12

13-17

VDDLOAD

100

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