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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PC8374L датащи(PDF) 27 Page - National Semiconductor (TI) |
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PC8374L датащи(HTML) 27 Page - National Semiconductor (TI) |
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27 / 239 page  1.0 Signal/Pin Connection and Description (Continued) Revision 1.1 27 www.national.com CC_DDCSDA 115 I/O SWSM VSB3 Chipset Cluster (2.5V or 3.3V) Level DDC Serial Data. SMBus serial data signal with 2.5V or 3.3V logic levels for DDC interface. External pull-up resistor to VDD3 or 2.5V is required. 5V_DDCSDA 116 I/O SWSM VSB3 5V Level DDC Serial Data. SMBus serial data signal with 5V logic levels for VGA monitor interface. External pull-up resistor to VDD5 is required. SMB1_SCL 87 I/O SWSM VSB3 Bus 1 Serial Clock. Serial clock signal of SMBus 1 (3.3V logic levels). External pull-up resistor to the 3.3V supply is required. SMB2_SCL 88 I/O SWSM VSB3 Bus 2 Serial Clock. Serial clock signal of SMBus 2 (3.3V logic levels). External pull-up resistor to the 3.3V supply is required. SMB1_SDA 89 I/O SWSM VSB3 Bus 1 Serial Data. Serial data signal of SMBus 1 (3.3V logic levels). External pull-up resistor to the 3.3V supply is required. SMB2_SDA 90 I/O SWSM VSB3 Bus 2 Serial Data. Serial data signal of SMBus 2 (3.3V logic levels). External pull-up resistor to the 3.3V supply is required. PCIRST_OUT 73 O O14/14 VSB3 PCI Reset Output. PCI system reset. PCIRST_OUT is a buffered copy of PCI_RESET when VDD3 is on, and it is held at low level when VDD3 is off. PCIRST_OUT2 74 O O14/14 VSB3 PCI Reset Output 2. PCI system reset (same behavior as PCIRST_OUT above). IDE_RSTDRV64 O OD6 VDD3 IDE Reset Output. IDE drive reset. IDE_RSTDRVisa buffered copy of PCI_RESET when VDD3 is on, and it is floating when VDD3 is off. Signal Pin(s) I/O Buffer Type Power Well Description Winbond Electronics Corp. Advanced PC Product Center |
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