PC8374L datasheet(60/239 Pages) NSC

60 / 239 page

3.0 Device Architecture and Configuration (Continued)

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3.8 FLOPPY DISK CONTROLLER (FDC) CONFIGURATION

3.8.1

General Description

The generic FDC is a standard FDC with a digital data separator and is DP8473 and N82077 software compatible. The

PC8374L FDC supports 14 of the 17 standard FDC signals described in the generic Floppy Disk Controller (FDC) chapter,

including the following (see Section 9.1 on page 192):

• FM and MFM modes are supported.

• A logic 1 is returned during LPC I/O read cycles by all register bits reflecting the state of floating (TRI-STATE) FDC pins.

Exceptions to standard FDC are:

• Automatic media sense using MSEN0 and MSEN1 signals is not supported.

• DRATE1 is not supported.

• DR1 is not supported.

• MTR1 is not supported.

The FDC functional block registers are shown in Section 9.1 on page 192. All of these registers are VDD3 powered.

3.8.2

Logical Device 0 (FDC) Configuration

Table 22 lists the configuration registers that affect the FDC. Only the last two registers (F0h and F1h) are described here.

See Section 3.2.3 on page 39 for descriptions of the other configuration registers. All of these registers are VDD3 powered.

Table 22. FDC Conﬁguration Register

Index

Conﬁguration Register or Action

Type

Power Well

Reset

30h

Activate (see Section 3.3.1 on page 48).

R/W

VDD3

00h

60h

Base Address MSB register. Bits 7-3 (for A15-11) are read-only, ‘00000’.

R/W

VDD3

03h

61h

Base Address LSB register. Bits 2 and 0 (for A2 and A0) are read-only, ‘00’.

R/W

VDD3

F2h

70h

Interrupt Number and Wake-Up on IRQ Enable register.

R/W

VDD3

06h

71h

Interrupt Type. Bit 1 is read/write; other bits are read-only.

R/W

VDD3

03h

74h

DMA Channel Select.

R/W

VDD3

02h

75h

Report no second DMA assignment.

VDD3

04h

F0h

FDC Conﬁguration register.

R/W

VDD3

24h

F1h

Drive ID register.

R/W

VDD3

00h

F8h

FDC Conﬁguration register (mirror of the register at index F0h).

R/W

VDD3

24h

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