PC8374L datasheet(35/239 Pages) NSC

35 / 239 page

2.0 Power, Reset and Clocks (Continued)

Revision 1.1

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Unless otherwise noted, reset references throughout the modules of the PC8374L devices default to the following resets:

● For V

BAT-retained functions (some SWC, Health Management configuration): VBAT Power-Up reset (within the limita-

tions described in Section 2.2.1).

● For V

SB3-powered functions (GPIO ports, SWC, Health Management, Glue Functions and some Conﬁguration

Control): VSB Power-Up reset (within the limitations described in Section 2.2.2).

● For V

DD3-powered functions (Legacy modules, LPC, on-chip Clock Generator and some Conﬁguration Control): VDD

Power-Up reset, Hardware Reset or Software Reset (within the limitations described in Sections 2.2.3, 2.2.4 and

2.2.5).

The following sections detail the sources and effects of the various PC8374L resets.

2.2.1

VBAT Power-Up Reset

VBAT Power-Up reset is generated by an internal circuit when VBAT power is applied, if VSB3 is off. An active VBAT Power-

Up reset signal is generated following a rise in the VBAT until the level of the VBAT power higher than VBATLOW is detected

(see Section 10.1.5 on page 213). A VBAT Power-Up reset is generated independently of the state of the VDD3 power supply.

When VBAT Power-Up reset is active, it resets the registers whose values are retained by VBAT (some of the SWC, Health

Management configuration).

2.2.2

VSB Power-Up Reset

VSB Power-Up reset is generated by an internal circuit when VSB3 power is applied. The VSB Power-Up reset time (tIRST)

lasts either 17 cycles of the 32 KHz clock domain or until the PCI_RESET signal is de-asserted, whichever occurs first. Ex-

ternal devices must wait at least tIRST before accessing the PC8374L device.

Note that the 32 KHz clock domain starts toggling t32KW +t32KVAL after VSB3 power-up. This delay must be added to the 17

clock cycles (see “Low-Frequency Clock Timing” on page 223).

VSB Power-Up reset performs the actions listed below and all the actions performed by VDD Power-Up reset (see

Section 2.2.3). Note that VDD3 must be active during VSB3 power-up for all VDD Power-Up reset actions to be performed:

• Puts pins with V

SB3 strap options into TRI-STATE and enables their internal pull-up resistors

• Samples the logic levels of the V

SB3 strap pins

• Samples the levels of the V

BAT power pin

• Activates the relevant circuits in SWC according to the level of the V

BAT power pin

• Loads default values to the V

BAT-powered bits, if VBAT is off

• Resets all lock bits in configuration registers, Health Management and SWC

• Loads default values to VDDLOAD bits in the GPIO configuration registers

• Loads default values to the V

SB3-powered bits in the configuration registers, SWC, Health Management and GPIO

• Sets up the pull-up or pull-down option and the default source for the V

SB3-powered multiplexed output pins

2.2.3

VDD Power-Up Reset

VDD Power-Up reset is generated by an internal circuit when VDD3 power is turned on. VDD Power-Up reset time (tIRST) lasts

until the PCI_RESET signal is de-asserted. The Hardware reset (PCI_RESET) must be asserted for a minimum of 10 ms to

ensure that the PC8374L device operates correctly.

External devices must wait at least tIRST before accessing the PC8374L. If the host processor accesses the PC8374L during

this time, the PC8374L LPC interface ignores the transaction (that is, it does not return a SYNC handshake).

VDD3 Power-Up reset performs the following actions:

• Puts pins with strap options into TRI-STATE and enables their internal pull-up resistors

• Samples the logic levels of the strap pins

• Executes all the actions performed by the Hardware reset (see Section 2.2.4)

2.2.4

Hardware Reset

Hardware reset is activated by the assertion (low) of the PCI_RESET input while VDD3 is “good”. When VDD3 power is off,

the PC8374L device ignores the level of the PCI_RESET input. However, the PCIRST_OUT and PCIRST_OUT2 outputs

reflect the PCI_RESET input and thus are active (low). In addition, the Hardware reset (PCI_RESET) must be asserted after

VSB power-up, as described in Section 2.2.2.

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