PC8374L datasheet(52/239 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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3.7 PC8374L CONFIGURATION REGISTERS

This section describes the PC8374L configuration and ID registers (i.e., registers with first level indexes in the range of 10h

−2Fh).

3.7.1

Memory Mapping Control Register (MEMMAP)

Power Well: VDD3

Location:

Index 10h

Type:

Varies per bit

Bit

Name

MEMEN

LOCKMEM

Reserved

BIODIS

LDMEMEN CFGMEMEN

Reset

Bit

Type

Description

R/W or

MEMEN (Memory Mapping Enable). When set to 1, enables memory mapping. MEMADR1 and

MEMADR2 registers must be configured before this bit is set to 1.

0: Memory mapping is disabled (default)

1: Memory mapping is enabled

R/W1S LOCKMEM (Lock Memory Mapping Conﬁguration). When set to 1, locks the configuration registers

of memory mapping: MEMMAP, MEMADR1 and MEMADR2. Once set, the bit can be cleared only by

VDD3 Power-Up reset.

0: R/W bits are enabled for write (default)

1: All bits of MEMMAP, MEMADR1 and MEMADR2 registers are RO

5-3

Reserved.

R/W or

BIODIS (I/O Base Address Disable). When set to 1, disables selected 2Eh/2Fh or 4Eh/4Fh addresses

acknowledged on LPC, and prevents any I/O transaction to PC8374L device. The bit disables the

PC8374L 2Eh/2Fh or 4Eh/4Fh I/O mapping only when MEMEN, LDMEMEN and CFGMEMEN bits are

all set to 1.

0: The 2Eh/2Fh or 4Eh/4Fh I/O mapping is enabled (default)

1: The 2Eh/2Fh or 4Eh/4Fh I/O mapping is disabled

R/W or

LDMEMEN (Enable Memory Mapping of Logical Devices Configuration Registers). When set to 1,

enables the memory mapping of Logical Devices Conﬁguration registers (I/O index 30h-FFh). When

cleared, all Logical Devices Conﬁguration registers are I/O mapped. The bit enables memory mapping

only when MEMEN bit is set to 1.

0: All Logical Devices Conﬁguration registers are I/O mapped (default)

1: All Logical Devices Conﬁguration registers are Memory mapped

Note: When this bit is 1 (and MEMEN is 1), I/O mapping of the Logical Devices Conﬁguration registers

is still enabled (in addition to the memory mapping) when BIODIS is 0 or CFGMEMEN is 0.

R/W or

CFGMEMEN (Enable Memory Mapping of Control and Configuration Registers). When set to 1,

enables the memory mapping of device control and conﬁguration registers (I/O index 10h-2Fh). When

cleared, the device control and conﬁguration registers are I/O mapped. The bit enables memory

mapping only when MEMEN bit is set to 1.

0: All control and configuration registers are I/O mapped (default).

1: All control and configuration registers are Memory mapped.

Note: When this bit is 1 (and MEMEN is 1), I/O mapping of the device control and conﬁguration regis-

ters is still enabled (in addition to the memory mapping) when BIODIS is 0 or LDMEMEN is 0.

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