PC8374L datasheet(43/239 Pages) NSC

43 / 239 page

3.0 Device Architecture and Configuration (Continued)

Revision 1.1

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SuperI/O Conﬁguration Registers

The PC8374L SuperI/O configuration registers at indexes 20h (SuperI/O ID) and 27h (SuperI/O Revision ID) are used for

part identification. The other configuration registers are used for global power management and selecting pin multiplexing

options. For details, see Section 3.7 on page 52.

Logical Device Control and Conﬁguration Registers

A subset of these registers is implemented for each logical device. See the functional block descriptions in the following sec-

tions.

Control Registers

The only implemented control register for each logical device is the Activate register at index 30h. Bit 0 of the Activate

register controls the activation of the associated functional block. Activation enables access to the functional block’s runtime

registers and attaches its system resources, which are unassigned as long as it is not activated. Other effects may apply on

a function-specific basis (such as clock enable and active pinout signaling). Access to the configuration register of the logical

device is enabled even when the logical device is not activated.

Standard Conﬁguration Registers

The standard configuration registers manage the PnP resource allocation to the functional blocks. The I/O port base address

descriptor 0 is a pair of registers at Index 60

−61h that hold the first 16-bit base address for the register set of the functional

block. An optional 16-bit second base-address (descriptor 1) at index 62

−63h is used for logical devices with more than one

continuous register set. Interrupt Number and Wake-Up on IRQ Enable (index 70h) and IRQ Type Select (index 71h) allocate

an IRQ line to the block and control its type. DMA Channel Select 0 (index 74h) allocates a DMA channel to the block, where

applicable. DMA Channel Select 1 (index 75h) allocates a second DMA channel, where applicable.

Vendor-Deﬁned Logical Device Conﬁguration Register

The vendor-defined logical device registers start at index F0h and control function-specific parameters such as operation

modes, power saving modes, pin TRI-STATE, clock rate selection and non-standard extensions to generic functions.

3.2.5

Default Configuration Setup

The default configuration setup of the PC8374L device is determined by the four reset types described in Section 2.2 on

page 34. See the specific register descriptions for the bits affected by each reset source.

In the event of a VSB3 Power-Up reset, the following default configuration is set up:

• All lock bits in the configuration registers are reset (the protected bits are unlocked).

• All the unlocked bits in the configuration registers powered by the V

SB3 plane are reset to their default values.

In the event of a VDD3 Power-Up (also induced by VSB3 Power-Up reset) or Hardware reset, the PC8374L device wakes up

with the following default configuration setup:

• The configuration base address is 2Eh or 4Eh, according to the BADDR strap pin value, as shown in Table 8 on page 38.

• All lock bits in the configuration registers are reset (the protected bits are unlocked).

• All the actions performed by the Software reset are executed.

If a Software reset occurs, the PC8374L device wakes up with the following default configuration setup:

• All the unlocked bits in the configuration registers powered by the V

DD3 plane are reset to their default values.

• All logical devices are disabled (the Activation bit is reset) and the V

SB3-powered logical devices (GPIO, SWC, and

Health Management) remain functional but their registers cannot be accessed by the host.

• Standard configuration registers of all logical devices are set to their default values.

• National Semiconductor proprietary functions are not assigned with any default resources, and the default values of their

base addresses are all 00h.

• All Legacy devices (Serial Ports, InfraRed Port, Parallel Port, Floppy Disk Controller, and Keyboard and Mouse Control-

ler) are reset. Default values are loaded into the Legacy module runtime registers.

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