PC8374L datasheet(38/239 Pages) NSC

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Device Architecture and Conﬁguration

The PC8374L SuperI/O device includes a collection of legacy and proprietary functional blocks. Each functional block is de-

scribed in a separate chapter. This chapter describes the structure of the PC8374L SuperI/O device and provides all logical

device specific information, including specific implementation of generic blocks, system interface and device configuration.

3.1 OVERVIEW

The PC8374L SuperI/O consists of the following: nine logical devices, the host interface, the Glue Functions and a central

set of configuration registers.

The host, via the LPC Bus interface, can access the modules. This interface supports I/O Read/Write, Memory Read/Write,

8-bit Memory Firmware Read/Write, and 8-bit DMA transactions of the LPC bus (see Section 5.2 on page 109).

The central configuration register set is ACPI compliant and supports PnP configuration. The configuration registers are struc-

tured as a subset of the Plug and Play Standard registers, defined in Appendix A of the Plug and Play ISA Specification, Re-

vision 1.0a by Intel® and Microsoft®. All system resources assigned to the functional blocks (Memory address space, I/O

address space, IRQ numbers and DMA channels) are configured in and managed by the central configuration register set. In

addition, some function-specific parameters are configurable through the configuration registers and distributed to the function-

al blocks through special control signals.

3.2 CONFIGURATION STRUCTURE AND ACCESS

The configuration structure is based on a set of banked registers that are accessed via a pair of specialized registers.

3.2.1

The Index-Data Register Pair

Access to the PC8374L configuration registers is via an Index-Data register pair, using only two system I/O byte locations.

The base address of this register pair is determined during reset according to the state of the hardware strapping option on

the BADDR pin. Table 8 shows the selected base addresses as a function of BADDR.

The Index register is an 8-bit read/write register located at the selected base address (Base+0). It is used as a pointer to the

configuration register file and holds the index of the configuration register that is currently accessible via the Data register.

Reading the Index register returns the last value written to it (or the default of 00h after reset).

The Data register is an 8-bit register (Base+1) used as a data path to any configuration register. Accessing the Data register

actually accesses the configuration register that is currently pointed to by the Index register.

3.2.2

Banked Logical Device Registers Structure

Each functional block is associated with a Logical Device Number (LDN). The configuration registers are grouped into banks,

where each bank holds the standard configuration registers of the corresponding logical device. Table 9 shows the LDN

values of the PC8374L functional blocks. Any value not listed is reserved.

Figure 4 shows the structure of the standard configuration register file. The LDN and PC8374L configuration registers are

not banked and are accessed by the Index-Data register pair only, as described above. However, the device control and

device configuration registers are duplicated over nine banks, corresponding to the nine logical devices. Therefore, access-

ing a specific register in a specific bank is performed by two-dimensional indexing, where the LDN register selects the bank

(or logical device) and the Index register selects the register within the bank. Accessing the Data register while the Index

register holds a value of 30h or higher actually accesses the configuration registers of the logical device selected by the LDN

Table 8. BADDR Strapping Options

BADDR

I/O Address

Index Register

Data Register

1 (default)

2Eh

2Fh

4Eh

4Fh

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