PC8374L datasheet(37/239 Pages) NSC

37 / 239 page

2.0 Power, Reset and Clocks (Continued)

Revision 1.1

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Speciﬁcations

Clock Generator wake-up time is 33 msec (maximum). This is measured from PCI_RESET deassertion until the internal 48

MHz clock is stable. When VDD3 exists, tolerance (long term deviation) of the output clock, relative to the 14.31818 MHz clock,

±110 ppm. Total tolerance is therefore ± (input reference clock tolerance + 110 ppm). Cycle-by-cycle variance is 0.4 nsec

(maximum). When only VSB3 exists, tolerance (long term deviation) of the output clock is ± 10%.

2.4 TESTABILITY SUPPORT

The PC8374L device supports two testing techniques:

• In-Circuit Testing (ICT)

• XOR Tree Testing

2.4.1

ICT

The In-Circuit Testing (ICT) technique, also known as “bed-of-nails”, injects logic patterns to the input pins of the devices

mounted on the tested board. It then checks their outputs for the correct logic levels.

The PC8374L supports this testing technique by floating (putting in TRI-STATE) all the device pins. This prevents “back-

driving” the PC8374L pins by the ICT tester when a device normally controlled by PC8374L is tested (device inputs are driv-

en by the ICT tester).

To enter TRI-STATE mode, the TRIS pin must be pulled low (by a 10 K

Ω resistor to VSS), and the TEST pin must be left

unconnected after both VDD3 and VSB3 power supplies are turned on. In addition, the PCI_RESET pin must be held low for

at least 10 ms (see “VSB Power-Up Reset” on page 219 and “VDD Power-Up Reset” on page 221). After PCI_RESET is de-

asserted, all the device output and I/O pins are floated (put in TRI-STATE); exceptions to this are the power supply pins

(VDD3,VSB3,VSS,VCORF,VBAT), analog pins (VSB5, REF5V, REF5V_STBY), RSMRST, which do not float in TRI-STATE

mode.

2.4.2

XOR Tree Testing

When the PC8374L device is mounted on a board, it can be tested using the XOR Tree technique. This test also checks the

correct connection of the device pins to the board.

To enter XOR Tree mode, the TEST pin must be pulled low (by a 10 K

Ω resistor to VSS), and the TRIS pin must be left

unconnected after both VDD3 and VSB3 power supplies are turned on. In addition, the PCI_RESET pin must be held low for

at least 10 ms (see “VSB Power-Up Reset” on page 219 and “VDD Power-Up Reset” on page 221). After PCI_RESET is de-

asserted, the device pins (including the PCI_RESET, TRIS and TEST pins) are connected in a XOR Tree configuration and

are isolated from the internal PC8374L functions.

In XOR Tree mode, all PC8374L device pins are configured as inputs, except the last pin in the tree, which is the XOR_OUT

output. The buffer type of the input pins participating in the XOR tree, is INT (Input, TTL compatible), regardless of the buffer

type of these pins in normal device operation mode (see Section 1.4 on page 21). The input pins are chained through XOR

gates, as shown in Figure 3. The power supply pins (VDD3,VSB3,VSS,VCORF,VBAT), the analog pins (VSB5, REF5V,

REF5V_STBY, RSMRST) and the not connected pins (NC) are excluded from the XOR tree.

Figure 3. XOR Tree (Simpliﬁed Diagram)

The XOR tree starts with pin 32, continues incrementally with pin 33 (the next pin in ascending order) through pins 128, 1,

and 28, and ends with pin 30 (XOR_OUT).

The maximum propagation delay through the XOR tree, from pin 32 to XOR_OUT is 200 ns.

VSUP

Pin 32

XOR_OUT

Pin 33

Pin 28

Pin 30

Pin 1

Pin 128

. . .

Winbond Electronics Corp. Advanced PC Product Center

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