PC8374L datasheet(44/239 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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3.2.6

Memory Space Mapping

The PC8374L device configuration registers and Logical Device registers can be mapped to either I/O or memory space.

The memory mapping control register (MEMMAP; see Section 3.7.1 on page 52) enables the device memory mapping, and

allows memory mapping of PC8374L control and configuration registers at I/O indexes 10h-2Fh, and logical device config-

uration registers at I/O indexes 30h-FFh. Each logical device register can be enabled separately for memory access by

memory base descriptor at I/O index 50h.

The memory base address MEM_BASE of the PC8374L device is determined by MEMADR1 and MEMADR2 registers,

which hold the high 15-bits of 32-bits memory address (see Section 3.7.2 and Section 3.7.3 on page 53). Address bit 31 is

reserved to 1; this limits the PC8374L device memory mapping to the high 2GB of memory space. Address bits 0-15 are

used for mapping of PC8374L device registers; this allows the PC8374L device a linear address space with total of 64K.

Note: The maximum value for MEM_BASE+64K should not exceed 4G-64K-1=FFFEFFFFh to avoid overlapping with the

BIOS memory area (see Figure 6 on page 45); that is, the maximum value of MEM_BASE should not exceed

FFFDFFFFh.

Operating System device drivers must be responsible for performing physical-to-virtual memory-address translation, includ-

ing allocation of selectors that point to the PC8374L device. The device may be accessed in Protected mode by creating a

selector with the physical address defined in MEMADR1 and MEMADR2 registers, and a maximum size of 64K.

Table 17 and Table 18 show how to access the memory mapped registers of PC8374L device. Table 17 shows the memory

address to registers of Logical Devices with one bank, such as GPIO. This method allows access to up to 1024 registers in

each Logical Device that is organized as one bank.

Table 18 shows the memory address to PC8374L device control and configuration registers and to registers of Logical De-

vices with several banks. This method allows access to up to 32 banks (and up to 32 registers in each bank) in Logical De-

vices that are organized in banks.

Window bit provides duplicate addresses for registers, to be used for read and write accesses. This resolves the problem of

PCI/LPC transaction buffering by some chip-sets. For example, this feature can be used to insure the order of transactions

for Write 1-to-Clear or Read-to-Clear registers.

Table 19 shows the Logical Device Number (LDN) field used by memory transactions for each PC8374L internal function

that can be enabled for memory transactions. Note that most of these LDNs are equivalent to those assigned by the plug-

and-play configuration, but they are not functionally identical.

Table 19. Logical Device Number (LDN) Assignment for Memory Space Mapping

Table 17. PC8374L Register Memory Address

24 23

Reserved

MEM_BASE

Window

Logical Device

Number

xxx xxxx

xxxx xxxx

xxx xx

xx xxxx xxxx

Table 18. PC8374L Register Memory Address to Logical Device with Register Banks

24 23

Reserved

MEM_BASE

Window

Logical Device

Number

Bank Number

xxx xxxx

xxxx xxxx

xxx xx

xx xxx

x xxxx

LDN

Functional Block

04h

System Wake-Up Control (SWC)

07h

General-Purpose I/O (GPIO) Ports

08h

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