PC8374L datasheet(82/239 Pages) NSC

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4.0 System Wake-Up Control (SWC) (Continued)

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Revision1.1

Figure 11. SWC Block Diagram

4.2 FUNCTIONAL DESCRIPTION

4.2.1

External Events

General-Purpose Input/Output Events

The PC8374L device supports 15 VSB3-powered General-Purpose Input/Output events through ports GPIOE00-07 and

GPIOE10-17 (excluding GPIO15). VDD3- and VSB3-powered signals can be connected to the GPIO pins to become sources

of external events. A VDD3-powered signal, when used to generate an event, is internally disabled for event generation while

VDD3 power is off. It is also disabled for event generation for tEWIV after VDD3 power is restored (see “Wake-Up Inputs at

VDD3 Power Switching” on page 236), which prevents the detection of false events during power transitions and while the

signal driver is not powered. For the same reasons, a VSB3-powered signal used to generate an event is enabled only tEWIV

after VSB3 power is on. (When VSB3 is off, the whole SWC module is disabled.)

Each GPIOE pin has both programmable polarity and an optional debouncer (see Figure 12). The debouncer is enabled

after the reset but can be disabled by software. The debouncing time is longer than 16 ms.

A GPIO event can generate the system interrupt (IRQ) if the event is both enabled and routed to IRQ. The status, event

enable and pending event routing bits to IRQ are implemented in the GPIO Port module (see Section 6.3 on page 113). The

status bit is set when an event of the programed type (edge or level) is detected.

A GPIO event can also generate the Power Management SCI interrupt (SIOPME). The status and event enable bits are im-

plemented in the SWC module (see Figures 12 and 13).

An active level-type event sets the status bit in registers GPE1_STS_0 for ports GPIOE07-00 and GPE1_STS_1 for ports

GPIOE17-10 (see Sections 4.4.4 and 4.4.5 on page 101). The status bit remains set even after the event becomes inactive.

The status bit is cleared only when the software writes 1 to the bit. If the event is still active when software writes 1, the status

bit remains set.

After changing the GPIOE1x pin multiplexing, clear the relevant bits in the GPE1_STS_1 register, to prevent false events

(caused by the pin multiplexing switch) from generating a wake-up event.

External

Events

SIOPME

SCI

Interrupt

Status

GRN_LED

YLW_LED

LED

Control

Debounce

and

Detection

Event

Status

Internal

Events

VDD3 Status

SPL_S3

SLP_S5

Keyboard

and Mouse

Detection

Event

Enable

SCI

Interrupt

Enable

(IRQ)

IRQ

Routing

Control

PWRGD_PS

Special

Management

VDD3, VSB3 Status

Power

SPL_S3

VBAT

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