PC8374L datasheet(34/239 Pages) NSC

34 / 239 page

2.0 Power, Reset and Clocks (Continued)

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Revision1.1

Ground Connection. The following items must be connected to the ground layer (VSS) as close to the device as possible:

• The ground return (V

SS) pins

• The decoupling capacitors of the Main power supply (V

DD3) pins

• The decoupling capacitors of the Standby power supply (V

SB3) pins

• The decoupling capacitor of the Standby 5V supply (V

SB5) pin

• The decoupling capacitor of the on-chip Core power converter (V

CORF) pin

• The decoupling capacitor of the Backup battery (V

BAT) pin

Note that a low-impedance ground layer also improves noise isolation.

Decoupling Capacitors. The following decoupling capacitors must be used in order to reduce EMI and ground bounce:

• Main power supply (V

DD3): Place one capacitor of 0.1 µF on each VDD3-VSS pin pair as close to the pin as possible. In

addition, place one 10

−47 µF tantalum capacitor on the common net as close to the chip as possible.

• Standby power supply (V

SB3): Place one capacitor of 0.1 µF on each VSB3-VSS pin pair as close to the pin as possible.

In addition, place one 10

−47 µF tantalum capacitor on the common net as close to the chip as possible.

• Standby 5V supply (V

SB5): Place one capacitor of 0.1 µF on the VSB5-VSS pin pair as close to the pin as possible.

• On-chip Core power converter (V

CORF): Place one 1 µF ceramic capacitor on the VCORF-VSS pin pair as close to the pin

as possible.

• Backup battery (V

BAT): Place one capacitor of 0.1 µF on the VBAT pin as close to the pin as possible.

Figure 2. Decoupling Capacitors Connection

2.2 RESET SOURCES AND TYPES

The PC8374L device has five reset sources:

• V

BAT Power-Up Reset - activated when VBAT is powered up, if VSB3 is off.

• V

SB Power-Up Reset - activated when VSB3 is powered up.

• V

DD Power-Up Reset - activated when VDD3 is powered up.

• Hardware Reset - activated when the PCI_RESET input is asserted (low).

• Software Reset - triggered by SWRST bit in SIOCF1 register (see Section 3.7.5 on page 54); SWRST bit is set by the

host through the LPC interface.

VDD3

0.1

µF

0.1

µF

0.1

µF

0.1

µF

VSS

VDD3

VSS

10-47

µF

Main 3.3V

VSB3

VSS

VSB3

VSS

0.1

µF

0.1

µF

0.1

µF

110

107

10-47

µF

Standby 3.3V

µF

VCORF

VSB5

0.1

µF

Standby 5V

Backup

0.1

µF

VBAT

Battery

PC8374L

Winbond Electronics Corp. Advanced PC Product Center

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