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IMX6SDLCEC датащи(PDF) 133 Page - NXP Semiconductors

номер детали IMX6SDLCEC
подробное описание детали  i.MX 6Solo/6DualLite Applications Processors for Consumer Products
PDF  169 Pages
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производитель  NXP [NXP Semiconductors]
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IMX6SDLCEC датащи(HTML) 133 Page - NXP Semiconductors

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Electrical Characteristics
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018
NXP Semiconductors
133
4.11.21.2 Receive Timing
Figure 100. USB HSIC Receive Waveform
4.11.22 USB PHY Parameters
This section describes the USB-OTG PHY and the USB Host port PHY parameters.
The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision
2.0 OTG, USB Host with the amendments below (On-The-Go and Embedded Host Supplement to the USB
Revision 2.0 Specification is not applicable to Host port).
USB ENGINEERING CHANGE NOTICE
— Title: 5V Short Circuit Withstand Requirement Change
— Applies to: Universal Serial Bus Specification, Revision 2.0
Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
USB ENGINEERING CHANGE NOTICE
— Title: Pull-up/Pull-down resistors
— Applies to: Universal Serial Bus Specification, Revision 2.0
USB ENGINEERING CHANGE NOTICE
— Title: Suspend Current Limit Changes
— Applies to: Universal Serial Bus Specification, Revision 2.0
USB ENGINEERING CHANGE NOTICE
— Title: USB 2.0 Phase Locked SOFs
— Applies to: Universal Serial Bus Specification, Revision 2.0
On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
Table 92. USB HSIC Receive Parameters1
1 The timings in the table are guaranteed when:
—AC I/O voltage is between 0.9x to 1x of the I/O supply
—DDR_SEL configuration bits of the I/O are set to (10)b
Name
Parameter
Min
Max
Unit
Comment
Tstrobe
strobe period
4.166
4.167
ns
Thold
data hold time
300
ps
Measured at 50% point
Tsetup
data setup time
365
ps
Measured at 50% point
Tslew
strobe/data rising/falling time
0.7
2
V/ns
Averaged from 30% – 70% points
USB_H_STROBE
USB_H_DATA
Thold
Tstrobe
Tsetup



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