IMX6SDLCEC datasheet(131/169 Pages) NXP

131 / 169 page

Electrical Characteristics

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

131

4.11.20.2.2

UART Receiver

Figure 96 depicts the RS-232 serial mode receive timing with 8 data bit/1 stop bit format. Table 88 lists

serial mode receive timing characteristics.

Figure 96. UART RS-232 Serial Mode Receive Timing Diagram

4.11.20.2.3 UART IrDA Mode Timing

The following subsections give the UART transmit and receive timings in IrDA mode.

UART IrDA Mode Transmitter

Figure 97 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 89 lists

the transmit timing characteristics.

Figure 97. UART IrDA Mode Transmit Timing Diagram

Table 88. RS-232 Serial Mode Receive Timing Parameters

Parameter

Symbol

Min

Max

Unit

UA2

Receive Bit Time1

1 The UART receiver can tolerate 1/(16 x Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not

exceed 3/(16

x Fbaud_rate).

tRbit

1/Fbaud_rate

2 - 1/(16 x F

baud_rate)

2 F

baud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

1/Fbaud_rate + 1/(16 x Fbaud_rate)—

Table 89. IrDA Mode Transmit Timing Parameters

Parameter

Symbol

Min

Max

Unit

UA3

Transmit Bit Time in IrDA mode

tTIRbit

1/Fbaud_rate

1 - T

ref_clk

1 F

baud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

2 T

ref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

1/Fbaud_rate + Tref_clk

—

UA4

Transmit IR Pulse Duration

tTIRpulse

(3/16) x (1/Fbaud_rate) - Tref_clk

(3/16) x (1/Fbaud_rate) + Tref_clk

—

Bit 1

Bit 2

Bit 0

Bit 4

Bit 5

Bit 6

Bit 7

UARTx_RX_DATA

(input)

Bit 3

Start

Bit

STOP

BIT

Start

Bit

Possible

Parity

Bit

Par Bit

UA2

Bit 1

Bit 2

Bit 0

Bit 4

Bit 5

Bit 6

Bit 7

UARTx_TX_DATA

(output)

Bit 3

Start

Bit

STOP

BIT

Possible

Parity

Bit

UA3

UA4

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