UPD360 datasheet(127/221 Pages) MICROCHIP

127 / 221 page

 2016-2017 Microchip Technology Inc.

DS00002084C-page 127

UPD360

11.4

Power Delivery MAC Registers

This section details the Power Delivery MAC registers. For an overview of the entire device register map, refer to Section

4.0, "Register Map," on page 19.

TABLE 11-5:

POWER DELIVERY MAC REGISTER MAP

Address

1800h – 1849h

PD MAC TX Queue/FIFO (74 bytes) (See Section 11.1.1, "TX Queue" for additional info)

184Ah – 18FFh

Reserved for future expansion

1900h – 197Fh

PD MAC RX FIFO (128 bytes) (See Section 11.2.1, "RX Queue" for additional info)

1980h – 19FFh

Reserved for future expansion

1A00h

TX Control Register A (TX_CTL_A)

1A01h

TX Status Register (TX_STAT)

1A02h

TX Parameters Register C (TX_PARAM_C)

1A03h

TX Packet Length Register (TX_PKT_LEN)

1A04h

TX Parameters Register A (TX_PARAM_A)

1A05h

TX Control Register B (TX_CTL_B)

1A06h

TX Parameters Register B (TX_PARAM_B)

1A07h

TX Bit-Time Count Register (TX_BITTIME_CNT)

1A08h

TX Turnaround Time Register (TX_TA_TIME)

1A09h

TX Abort Status Register (TX_ABORT_STAT)

1A0Ah

TX Auto-Response Abort Status Register (TX_AR_ABORT_STAT)

1A0Bh

TX Power Up Time Register (TX_POWER_UP_TIME)

1A0Ch

TX Power Down Time Register (TX_POWER_DOWN_TIME)

1A0Dh – 1A3Fh

Reserved for future expansion

1A40h

RX Control Register A (RX_CTL_A)

1A41h

RX Control Register B (RX_CTL_B)

1A42h

RX Maximum Bit-Rate Bit Period Count Register (RX_BIT_PER_CNT_MAX_BR)

1A43h

RX Minimum Bit-Rate Bit Period Count Register (RX_BIT_PER_CNT_MIN_BR)

1A44h

RX Status Register (RX_STAT)

1A45h

RX Packet Status Register (RX_PKT_STAT)

1A46h

RX tReceive Time Register (RX_TRECEIVE_TIME)

1A47h

RX BadCRC Packet Count Register (RX_BADCRC_PKT_CNT)

1A48h

RX Duplicate Packet Count Register (RX_DUP_PKT_CNT)

1A49h

RX Hard Reset Detection Window Register (RX_HR_DET_WINDOW)

1A4Ah

RX Last GoodCRC Packet High Byte Register (RX_LAST_GCRC_PKT_HI)

1A4Bh

RX Last GoodCRC Packet Low Byte Register (RX_LAST_GCRC_PKT_LO)

1A4Ch

RX Message ID Stored Register (RX_MSG_ID_STORED)

1A4Dh

RX Maximum Packet Size Register (RX_MAX_SIZE)

1A4Eh – 1A4Fh

Reserved for future expansion

1A50h

RX FIFO Read Pointer Register (RX_FIFO_RD_PTR)

1A51h

RX FIFO Read Pointer Control Bits Register (RX_FIFO_RD_PTR_CTL_BITS)

1A52h

RX FIFO Write Current Pointer Register (RX_FIFO_WR_CURRENT_PTR)

1A53h

RX FIFO Write Current Pointer Control Bits Register

(RX_FIFO_WR_CURRENT_PTR_CTL_BITS)

1A54h

RX FIFO Write Head Pointer Register (RX_FIFO_WR_HEAD_PTR)

1A55h

RX FIFO Write Head Pointer Control Bits Register (RX_FIFO_WR_HEAD_PTR_CTL_BITS)

1A56h

RX FIFO Write Head Pointer Plus One Register (RX_FIFO_WR_HEAD_PTR_PLUS_ONE)

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