UPD360 datasheet(126/221 Pages) MICROCHIP

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UPD360

DS00002084C-page 126

 2016-2017 Microchip Technology Inc.

11.3

PD MAC BIST

The PD MAC incorporates BIST functions as defined in the USB PD Specification. It is comprised of a TX and RX block.

The BIST TX block contains a PRBS (Pseudo Random Binary Sequence) generator, BIST pattern generation logic, and

its own bit-timing logic. The SOP type used by TX BIST Test Frames is a 20-bit static vector which is created by multi-

plexing between the five SOP ordered sets based on a register setting. The resultant 20-bit vector is simply bit selected

when the packet is transmitted.

BIST TX is entered when the BIST_EN bit in the BIST Control Register A (BIST_CTL_A) is set along with BIST_RX_EN

being clear. The BIST TX mode (TX type) is set using the BIST_TX_MODE field of the BIST Control Register A

(BIST_CTL_A) and is started by first using the BIST_TX_RST bit and then by using the BIST_TX_START/BIST_TX-

_STATUS bit of the BIST Control Register B (BIST_CTL_B). Continuous BIST transmission (modes 0, 1, 2, 3, and 5)

should be stopped by first using the BIST_TX_RST bit before clearing the BIST_EN bit. It may take up to 1 bit time for

the TX to stop. BIST_EN should not be cleared until after this time.

The BIST RX block contains a PRBS generator and bit error detection logic. BIST RX is used only during the BIST

Receiver Test. BIST RX is entered when the BIST_EN bit in the BIST Control Register A (BIST_CTL_A) is set along

with BIST_RX_EN. The BIST error counter is reset using the BIST_CLR_ERR_CNT bit of the BIST Control Register B

(BIST_CTL_B).

For information on the BIST registers, refer to Section 11.4.5, "PD MAC BIST Registers," on page 168.

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