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UPD360 датащи(PDF) 58 Page - Microchip Technology |
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UPD360 датащи(HTML) 58 Page - Microchip Technology |
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58 / 221 page ![]() UPD360 DS00002084C-page 58 2016-2017 Microchip Technology Inc. 8.5.23 CONFIGURE PIO OUTPUT REGISTER (CFG_PIO_OUT) This register enables multiple PIO output values to be updated in a single CSR write. 8.5.24 CONFIGURE PIO OUTPUT UPDATE REGISTER (CFG_PIO_OUT_UPD) 8.5.25 PIO OVERRIDE X OUTPUT ENABLE REGISTERS (PIO_OVRX_OUT_EN) Address: 0059h Size: 16 bits Bits Description Type Default 15:0 CFG_PIO_OUT When this register is written, the output values for the respective PIOs are updated. Specifically, the DataOutput in the respective CFG_PIOx registers are updated. This register is not updated until the byte located at 005Ah is written by soft- ware. This is to prevent placing externally driven components in an invalid state while updating. R/W 0000h Address: 005Bh Size: 16 bits Bits Description Type Default 15:0 CFG_PIO_OUTx_UPD R/W 0000h Address: x=0: 0060h x=1: 0062h x=2: 0064h x=3: 0066h Size: 16 bits Bits Description Type Default 15:0 PIO_OVR_OUT_EN_X Each of the overrides has an instance of this CSR to indicate which PIO out- puts are controlled by it. When asserted associated PIO output’s state is con- trolled by the respective override function. Note: The same PIO output can be enabled by multiple overrides. R/W 0h |
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