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UPD360 датащи(PDF) 51 Page - Microchip Technology |
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UPD360 датащи(HTML) 51 Page - Microchip Technology |
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51 / 221 page ![]() 2016-2017 Microchip Technology Inc. DS00002084C-page 51 UPD360 8.5.14 PIO INTERRUPT ENABLE REGISTER (PIO_INT_EN) 8.5.15 CONFIGURE PIOX REGISTERS (CFG_PIOX) Address: 0024h Size: 16 bits Bits Description Type Default 15:0 PIO_EN[15:0] When set, an interrupt can be generated on a state change from the corre- sponding PIO line. R/W 0h Address: x=0: 0030h x=1: 0031h x=2: 0032h x=3: 0033h x=4: 0034h x=5: 0035h x=6: 0036h x=7: 0037h x=8: 0038h x=9: 0039h x=10: 003Ah x=11: 003Bh x=12: 003Ch x=13: 003Dh x=14: 003Eh x=15: 003Fh Size: 8 bits Bits Description Type Default 7 PullUpEnable 0b: No pull-up 1b: Pull-up enabled. R/W 0b 6 PullDownEnable 0b: No pull-down 1b: Pull-down enabled. R/W 0b 5 FallingAlert 0b: No alert on falling edge 1b: Assert PIO_INT on falling edge R/W 0b 4 RisingAlert 0b: No alert on rising edge 1b: Assert PIO_INT on rising edge R/W 0b 3 DataOutput 0b: Inactive (low for push-pull or open-drain) 1b: Active (high for push-pull, high-z for open-drain) Note: The input buffer status can be determined from the respective bit in PIO Status Register (PIO_STS). Note: The associated PIO output bit in the Configure PIO Output Regis- ter (CFG_PIO_OUT) will be updated to match the value written to this bit. R/W 0b |
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