UPD360 datasheet(74/221 Pages) MICROCHIP

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UPD360

DS00002084C-page 74

 2016-2017 Microchip Technology Inc.

9.3

UFP Operation

When operating as a UFP, the device applies an Rd pull-down on both CC lines and waits for a DFP connection from

the assertion of VBUS. The CC comparator is used to determine the advertised current charger capabilities supported

by the DFP.

9.3.1

SINK ATTACH DETECTION

The following steps illustrate how the device may be programmed to detect an attachment when operating as a Sink.

The following discussion does not cover dead-battery cases, which are described in Section 9.6, "Dead Battery".

Software accesses the device via I2C/SPI which wakes the device up and enables the 48 MHz oscillator.

Software programs the CC Comparator Control to 00b and disables the CC debouncer.

Software programs the VBUS Comparator Control to 00b and disables the VBUS debouncer.

Software polls CC_DB_ACTIVE and VBUS_DB_ACTIVE until they read back 0b to indicate that the CC

debouncer and VBUS debouncer are inactive. Software programs the Match Debounce Register (MATCH_DEB)

as required for the tPDDebounce interval.

Software programs the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) as required to match the

thresholds of interest.

Software programs the CC1 Pull-Down Value and CC2 Pull-Down Value in the CC Control Register (CC_CTL)

to advertise trimmed Rd.

Software enables CC_MATCH_VLD, CC1_MATCH_CHG or CC2_MATCH_CHG interrupt via the CC Interrupt

Enable Register (CC_INT_EN).

Assertion of CC_MATCH_VLD indicates that the initial CC debounce of both CC pins has completed and a valid

value is available in the CCx Match Registers (CCx_MATCH).

Software programs the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) as required to enable the

respective threshold(s) debouncing.

10. Software enables VBUS_INT to detect VBUS by configuring the VBUS Match Register (VBUS_MATCH).

11. Software enables VBUS_MATCH_VLD by configuring the Power Interrupt Enable Register (PWR_INT_EN).

12. Software enables IRQ_N via configured respective bits, for CC_INT, PWR_INT and VBUS_INT, in the Interrupt

Enable Register (INT_EN).

13. Software programs the CC Comparator Control to sample both CC pins.

14. Software programs VBUS Comparator/DAC to detect vSafe5V via the VBUS Comparator Control in the VBUS

Control Register (VBUS_CTL) and setting VBUS_THR0 and VBUS_THR1 via the VBUS Threshold x Registers

(VBUS_THRx).

15. Software turns off all clock sources with the exception of 20 KHz keep-alive clock via Clock Control Register

(CLK_CTL) to save power.

16. Upon connection to a partner DFP VBUS is powered to 5V.

17. After the programmed debounce interval, the respective CCx Change Status Registers (CCx_CHG_STS) is

updated and the respective CC1_MATCH_CHG or CC2_MATCH_CHG interrupt asserts which in turn asserts

CC_INT which in turn asserts IRQ_N.

18. VBUS is detected by the VBUS_DET comparator and debounced for the period defined by the VBUS Debounce

19. Software must debounce the CC match for tCCDebounce and VBUS for the PD Debounce Register (PD_DEB)

in order to detect the attach condition.

20. After attachment, software configures CC Communication Select in the CC Control Register (CC_CTL) to appro-

priately connect the baseband interface to the CC with the Rp pull-up if PD communication is desired.

21. DFP may communicate with the device.

Note:

Assertion of CC_MATCH_VLD indicates that the initial CC debounce of both CC pins has completed and

a valid value is available in the CCx Match Registers (CCx_MATCH).

Note:

Assertion of VBUS_MATCH_VLD indicates that the initial CC debounce of both CC pins has completed

and a valid value is available in the VBUS Match Register (VBUS_MATCH).

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