UPD360 datasheet(20/221 Pages) MICROCHIP

20 / 221 page

UPD360

DS00002084C-page 20

 2016-2017 Microchip Technology Inc.

5.0

I2C SLAVE CONTROLLER (UPD360-A/UPD360-B ONLY)

This chapter details the integrated I2C slave controller (I2C_DAT and I2C_CLK) available in the UPD360-A (+1.8V sig-

naling) and UPD360-B (+3.3V signaling). The I2C slave controller can be used for Host CPU serial management and

data transfer, and allows host access to all device Configuration and Status Registers (Section 4.0, "Register Map," on

page 19).

5.1

I2C Overview

I2C is a bi-directional 2-wire data protocol. A device that is currently sending data is defined as the “transmitter” and a

device that is currently receiving data is defined as the “receiver”. The bus is controlled by a master which generates

the SCL clock, controls bus access, and generates the start and stop conditions. The master and slave will operate as

transmitter or receiver, bit-by-bit, as determined by the master. Since the device I2C controller is a slave only, the terms

“host” and “master” are synonymous, both referring to the external side of the interface.

Both the clock (SCL) and data (SDA) signals have analog input filters that reject pulses that are less than 50 ns. The

data pin is driven low when either interface sends a low, emulating the wired-AND function of the I2C bus. Since the

slave interface never drives the clock pin, the wired-AND is not necessary.

The following bus states exist:

• Idle: Both I2C_DAT and I2C_CLK are high when the bus is idle.

• Start & Stop Conditions: A start condition (S) is defined as a high to low transition on the SDA line while SCL is

high. A stop condition (P) is defined as a low to high transition on the SDA line while SCL is high. The bus is con-

sidered to be busy following a start condition and is considered free 4.7 µs / 1.3 µs / 0.5µs (for 100 kHz / 400 kHz

/ 1MHz operation, respectively) following a stop condition. The bus stays busy following a repeated start condition

(Sr) in the absence of a stop condition. Stop/start sequences and repeated starts are otherwise functionally equiv-

alent.

• Data Valid: Data is valid, following the start condition, when SDA is stable while SCL is high. Data can only be

changed while the clock is low. There is one valid bit per clock pulse. Every byte must be 8 bits long and is trans-

mitted MSB first.

• Acknowledge: Each byte of data is followed by an acknowledge bit. The master generates a ninth clock pulse for

this bit, and the transmitter releases SDA (high). To provide a positive “acknowledge” (ACK), the receiver drives

SDA low so that it remains valid during the high period of the clock, taking into account the setup and hold times.

To provide a negative “no-acknowledge” (NACK or ACK), the receiver will allow the line to remain high during this

bit time. The receiver may be the master or the slave depending on the direction of the data. Typically the receiver

acknowledges each byte. If the master is the receiver, it does not generate an acknowledge on the last byte of a

transfer. This informs the slave to not drive the next byte of data, freeing SDA so that the master may generate a

stop or repeated start condition.

Figure 5-1 displays the various bus states of a typical I2C cycle.

FIGURE 5-1:

I2C CYCLES

I2C_DAT

I2C_CLK

Start Condition

Stop Condition

Data Valid

or Ack

Data Valid

or Ack

data

stable

data

can

change

data

stable

data

can

change

Re-Start

Condition

data

can

change

data

can

change

UPD360 датащи(PDF) 20 Page - Microchip Technology

UPD360 датащи(HTML) 20 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL