UPD360 datasheet(125/221 Pages) MICROCHIP

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 2016-2017 Microchip Technology Inc.

DS00002084C-page 125

UPD360

11.2.3.2

RX DES (De-serializer)

The RX DES converts the received serial bit stream from the CDR into 5bit symbols, identifies and generates start-of-

packet/end-of-packet/hard and cable reset signals, and decodes the symbols to 4b data.

11.2.3.2.1

SOP Detection

The SOP is detected by comparing the four most recently received 5-bit symbols to the expected SOP pattern. Per the

USB PD specification, detection of 3 of the 4 SOP symbols is sufficient. This is done by creating four unique groups

each containing three received symbols ({a,b,c}, {a,b,d}, {a,c,d} and {b,c,d}) with each group independently compared

to its respective symbols. Any successful match indicates an SOP.

There is a separate compare for each SOP type, enabled by the RX_SOP_ENABLE field in the RX Control Register B

(RX_CTL_B). The results are OR'ed. The SOP type is saved and used in the packet processing (auto reply, auto

response and queue status). Software is allowed to change the RX_SOP_ENABLE field at any time. The internal value

is held during active receive and updated from the register during idle time.

For generation of the RX_SOP interrupts in the RX SOP Interrupt Status Register (RX_SOP_IRQ_STAT), each SOP

detection is decoded but is not AND'ed with its RX_SOP_ENABLE.

11.2.3.2.2

Reset Detection

Hard and Cable resets are detected by comparing the four most recently received 5-bit symbols to the expected pat-

terns. Per the USB PD specification, detection of 3 of the 4 symbols is sufficient. This is done by creating four unique

groups each containing three received symbols ({a,b,c}, {a,b,d}, {a,c,d} and {b,c,d}) with each group independently com-

pared to its respective symbols. Any successful match indicates a Hard or Cable reset respectively.

Cable Reset must be enabled via the EN_CABLE_RESET bit in the RX Control Register A (RX_CTL_A).

11.2.3.3

RX CRC32

The receive data CRC32 is computed by the RX CRC32 module. The same logic used for TX CRC generation is utilized

to calculate the RX CRC.

The coded nibble data is streamed into the RX CRC32 one nibble at a time for CRC calculation. When the packet ends,

the output of this module represents the computed CRC for the received packet. A value of 0xC704_DD7B indicates a

good CRC. Detection of a valid EOP symbol latches the CRC value. The latched value is compared with the expected

good CRC residue value, which is used by the RX Queue to determine if the RX Queue status should be updated to

reflect valid data or not.

Note:

Note that only valid D-codes are processed to be written to the RX Queue. An invalid/reserved code is sim-

ply dropped.

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