UPD360 datasheet(21/221 Pages) MICROCHIP

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DS00002084C-page 21

UPD360

5.2

I2C Slave Operation

The I2C slave serial interface consists of a data wire (I2C_DAT) and a serial clock (I2C_CLK). The serial clock is driven

by the master, while the data wire is bi-directional. Both signals are open-drain and require external pull-up resistors.

The I2C slave controller implements the low level I2C slave serial interface (start and stop condition detection, data bit

transmission/reception and acknowledge generation/reception), handles the slave command protocol and performs

system register reads and writes. It tolerates and also provides clock stretching, in particular for supporting a transparent

Wake on Host Access (see Section 7.3, "Asynchronous I2C Wakeup (UPD360-A/UPD360-B Only)," on page 32).

The I2C slave controller conforms to the NXP I2C-Bus Specification (UM10204, April 4, 2014), and supports traffic as

defined therein for the following modes:

• Standard-mode (Sm, 100 kbit/s)

• Fast-mode (Fm, 400 kbit/s)

• Fast-mode Plus (Fm+, 1 Mbit/s)

Refer to Section 16.6.2, "I2C Slave Interface (UPD360-A/UPD360-B only)," on page 210 for timing information.

5.2.1

I2C SLAVE COMMAND FORMAT

The I2C slave serial interface supports single register and multiple register Read and Write commands. A Read or Write

command is started by the master first sending a Start condition, followed by a Control byte. The Control byte consists

of a 7-bit slave address and a 1-bit Read/Write indication (R/~W). The default slave address used by the device is

selected via the CFG_SEL1 configuration strap. Assuming the slave address in the Control byte matches this address,

the Control byte is acknowledged by the device. Otherwise, the entire sequence is ignored until the next Start condition.

The I2C slave controller also supports the General Call Address. The I2C command formats can be seen in Figure 5-2,

Figure 5-4, and Figure 5-5.

If the read/write indication (R/~W) in the Control byte is a 0 (Write), the next two bytes sent by the master are a register

address, and these two bytes are mandatory. The upper (first) two bits of the address field are a Direction control (DIR),

which indicates whether multi-byte accesses will increment, decrement, or fix (as static) the issued address

(Section 5.2.2). After the address bytes are acknowledged by the device, the master may send data bytes, which will

be written to successive registers starting at this address. It may instead send another Start condition (to start the read-

ing of data) or a Stop condition (only setting the address). The latter two will terminate the current Write before writing

any data, but will have the effect of setting the internal register address which will be used for subsequent Reads.

If the read/write indication (R/~W) in the Control byte is a 1 (Read), the device will start sending data following the Con-

trol byte acknowledge bit. Read commands cannot designate an address by themselves, but may optionally be prefixed

with a Write command to set it (see Figure 5-4, prefixes in gray). If however the Read immediately follows a Multiple

so this Read will start its access at the next successive byte address. Also, regardless of the previous access, a multiple-

byte Read will continue the Increment/Decrement internally, as determined by the previously-issued DIR field

(Section 5.2.2).

The length of the register address field is always two full bytes. Some high-order bits are don’t-care. Don’t-care register

address bits should be sent as ‘0’ always, for upward compatibility.

FIGURE 5-2:

I2C SLAVE ADDRESSING

R/~W

Control Byte

Address Byte 1

Start or

Stop or

Data [7]

DIR

Address Byte 0

13 12 11 10

Inc /

Dec /

Static

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