UPD360 datasheet(130/221 Pages) MICROCHIP

130 / 221 page

UPD360

DS00002084C-page 130

 2016-2017 Microchip Technology Inc.

WAIT4LINE_IDLE

Normally hardware will abort a TX packet (including all retry attempt) if the line

is Busy when hardware attempts to transmit the packet. (Note that transmis-

sion of GoodCRC ACK in response for Soft Reset is an exception to this, see

the DIS_SPCL_SR_GCRC_ACK bit.)

Setting this bit will force hardware to not abort the transmission, but rather

wait until line becomes idle and then transmit the message. The

RETRY_ON_LINE_BUSY option has lower priority then this function.

The following conditions will still abort the TX packet:

• Hard reset received

• Cable reset received (if enabled and the SOP type of the pending TX is

SOP', or SOP'', SOP'_Debug or SOP''_Debug)

• Good, non-duplicate packet, non-Ping, non-GoodCRC (including soft-

reset) received with RX and TX SOP types matching or RX SOP type

equaling SOP with TX SOP type not equaling SOP (can be disabled)

• Software sets the ABORT bit in the TX Control Register B (TX_CTL_B).

R/W

EN_AUTO_RSP_MODE

Enable automatic sending of GoodCRC message and BIST Error Count mes-

sage by hardware.

0: Auto GoodCRC Message disabled (default)

1: Auto GoodCRC Message enabled

Note:

Disabling Auto Response Mode will also disable automatic retry by

hardware, i.e., hardware will ignore the N_RETRY_CNT field of the

TX Parameters Register C (TX_PARAM_C).

R/W

EN_FMQ

Enable FIFO Mode queuing on the TX Queue's write interface.

0: Buffer Mode - TX Queue is accessed like a buffer/CSR (Default)

1: FIFO Mode

R/W

EN_RMDP

Enable Raw Mode Data Processing.

0: Automatic Mode Data Processing (default)

1: Enable Raw Mode Data Processing

R/W

Bits

Description

Type

Default

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