UPD360 datasheet(95/221 Pages) MICROCHIP

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DS00002084C-page 95

UPD360

9.12.16

VCONN OCS AND BACK-DRIVE DEBOUNCE REGISTER (VCONN_DEB)

9.12.17

CCX DEBOUNCE CLEAR ENABLE REGISTERS (CCX_DBCLR_EN)

Note 9-5

The default depends on the device’s configuration, as shown in table Table 9-10 which depends upon

CFG_SEL0, PWR_CAP0, and PWR_CAP1 pins.

APPLICATION NOTE: Clearing a bit in CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) shall cause the

respective bit in CCx Match Registers (CCx_MATCH) to be immediately updated upon a

change in state of the associated threshold. This causes a state change in CCx Change

Status Registers (CCx_CHG_STS) and assertion of CC_INT, if enabled. To prevent this CCx

Match Enable Registers (CCx_MATCH_EN) should be updated before the CCx Debounce

Clear Enable Registers (CCx_DBCLR_EN) by having the associated threshold cleared.

Address:

0819h

Size:

8 bits

Bits

Description

Type

Default

7:0

VCONN and Back-Drive Debounce (VCONN_DEB)

Period used for implementing debounce of over-current detected on VCONN

FET as well as back-drive detected on the CC pins.

Note:

This register has units of 1 ms.

Note:

This register should not be changed when VCONN OCS Enable is

set.

R/W

Address:

x=1: 081Ah

x=2: 081Bh

Size:

8 bits

Bits

Description

Type

Default

7:0

CC Debounce Clear Enable (CC_DBCLR_DEB)

When a bit is set, the respective threshold shall be included in the CC

debouncer. Alternatively, when cleared the respective threshold shall no lon-

ger be considered by the debouncer.

When CCx_DBCLR_EN bits are set on-the-fly, if a mismatch between the cur-

rent raw match vector (for the new CCx_DBCLR_EN) and the previous raw

match vector (for the old CCx_DBCLR_EN) exists, the DB will be reset.

Note:

Clearing bits in this register at run time does not reset the

debouncer.

Note:

The CC debouncer encompasses both CC1/CC2 pins. A detected

change for a threshold on either pin results in the debouncer reset-

ting.

Note:

Even though this register may change on-the-fly, the internal logic

will enable the change only at the end of the scan cycle, which is a

function of whether the CC1/CC2 pins are actively sampled and the

CCx Sample Enable Registers (CCx_SAMP_EN).

R/W

Note 9-5

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