UPD360 datasheet(124/221 Pages) MICROCHIP

124 / 221 page

UPD360

DS00002084C-page 124

 2016-2017 Microchip Technology Inc.

All pointers and status bits are readable by the software. All pointers and wrap around status bits are writable by the

software. Software is responsible for maintaining coherency between the pointer and the wrap toggle values.

The FIFO pointers can be reset by setting and clearing the RST_RECEIVER bit in the RX Control Register A (RX_CT-

L_A).

Each entry in the RX FIFO represents a byte of received data. Data written to the FIFO is the header, the payload, and

the CRC32. As stated earlier, only 5b symbols that correspond to valid D-codes are processed and written to the RX

Queue. K-Codes cannot be passed to the RX Queue, i.e., there is no “Raw Mode” receive capability. Software will see

de-framed packets only.

As mentioned earlier, the data in FIFO is the actual data and not symbols so it can be processed by software directly.

Corrupted packets are not written to the Queue.

11.2.2

RX CONTROL

RX Control implements the logic necessary for validating a received packet, updating the RX Queue status, and trigger-

ing automatic responses, if required.

11.2.2.1

Duplicate Packet Detection

For duplicate packet detection, the device maintains the last message ID received per SOP type. A flag (first_msg) is

maintained per SOP type and indicates if the stored last message ID is valid (there has been a previous packet). This

information is used when a good packet is received to detect if the message ID matches the last one received for that

SOP type.

The device stores the current message ID into the appropriate last message ID (as selected by the SOP of the current

received packet). The message ID and flag for a specified SOP type can be reset via the RX Message ID Stored Reg-

ister (RX_MSG_ID_STORED). All bits are cleared when software issues a SW_RESET or PD_RESET via the Reset

Control Register (RESET_CTL).

11.2.2.2

RX Control of Transmit Abort

Although the actual aborting of pending transmission is done by the Transmit Control block, it is the RX Control block

that makes the decision.

For pending transmissions (transmission triggered but waiting for bus idle or the bus turnaround time), the RX control

block generates a pulse at the EOP. It checks 1) that the packet is a good packet (good CRC, proper nibble alignment

and no symbol errors), 2) that the packet is not a Ping or GoodCRC message, 3a) that the SOP type of the received

packet matches the SOP type of the pending transmission or 3b) the SOP type of the received packet is SOP with the

SOP type of pending transmission being non-SOP (the latter can be disabled via the DIS_SOP_ABRTS_NON_SOP bit

in the TX Control Register A (TX_CTL_A)) and 4) that the packet is not a duplicate or is a Soft-Reset message.

For completed transmissions that are waiting for a GoodCRC to be returned, the RX Control checks 1) that the packet

is a good packet (good CRC, proper nibble alignment and no symbol errors), 2) that the packet is a Soft-Reset or is not

a GoodCRC message, 3a) that the SOP type of the received packet matches the SOP type of the pending transmission

or 3b) the SOP type of the received packet is SOP with the SOP type of pending transmission being non-SOP (the latter

can be disabled via the DIS_SOP_ABRTS_NON_SOP bit in the TX Control Register A (TX_CTL_A)) and 4) that the

packet is not a duplicate.

11.2.3

RX COMM

The RX Comm is comprised of the clock and data recovery (CDR), RX DES (de-serializer) (serial-to-parallel converter,

4b5b decoder, and framing detector), RX CRC32 (CRC calculator, receive timer), and other logic to detect valid packet

reception.

11.2.3.1

CDR

The BMC decodes the received data and outputs the bit stream signal. This signal is applied to the input of CDR module

which locks (period and phase) on to the data stream during the preamble phase and outputs the serial data and a cap-

ture strobe centered in the data window.

The CDR relies on edge-to-edge time measurement (two bit-times) during the preamble phase for period lock. An aver-

age of four successive good period measurements is used for period lock. Valid period measurement is determined by

the range specified by the RX Maximum Bit-Rate Bit Period Count Register (RX_BIT_PER_CNT_MAX_BR) and RX

Minimum Bit-Rate Bit Period Count Register (RX_BIT_PER_CNT_MIN_BR). Phase lock is achieved by comparing in-

phase and quadrature data samples to determine whether the phase needs to be advanced or retarded.

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