UPD360 datasheet(128/221 Pages) MICROCHIP

128 / 221 page

UPD360

DS00002084C-page 128

 2016-2017 Microchip Technology Inc.

1A57h

RX FIFO Write Head Pointer Plus One Control Bits Register

(RX_FIFO_WR_HEAD_PTR_PLUS_ONE_CTL_BITS)

1A58h – 1A7Fh

Reserved for future expansion

1A80h

MAC Interrupt Status Register (MAC_IRQ_STAT)

1A81h

TX Interrupt Status Register (TX_IRQ_STAT)

1A82h

RX Interrupt Status Register (RX_IRQ_STAT)

1A83h

RX Error Interrupt Status Register (RX_ERR_IRQ_STAT)

1A84h

Power Management Interrupt Status Register (PM_IRQ_STAT)

1A85h

RX SOP Interrupt Status Register (RX_SOP_IRQ_STAT)

1A86h

TX Interrupt Enable Register (TX_IRQ_EN)

1A87h

RX Interrupt Enable Register (RX_IRQ_EN)

1A88h

RX Error Interrupt Enable Register (RX_ERR_IRQ_EN)

1A89h

Power Management Interrupt Enable and Control Register (PM_IRQ_EN)

1A8Ah

RX SOP Interrupt Enable Register (RX_SOP_IRQ_EN)

1A8Bh

Reset Control Register (RESET_CTL)

1A8Ch – 1A9Fh

Reserved for future expansion

1AA0h

BMC RX High Level Full Bit Maximum Time Register (BMC_RX_HI_FB_MAX_TIME)

1AA1h

BMC RX High Level Full Bit Minimum Time Register (BMC_RX_HI_FB_MIN_TIME)

1AA2h

BMC RX Low Level Full Bit Maximum Time Register (BMC_RX_LO_FB_MAX_TIME)

1AA3h

BMC RX Low Level Full Bit Minimum Time Register (BMC_RX_LO_FB_MIN_TIME)

1AA4h

BMC RX High Level Half Bit Maximum Time Register (BMC_RX_HI_HB_MAX_TIME)

1AA5h

BMC RX High Level Half Bit Minimum Time Register (BMC_RX_HI_HB_MIN_TIME)

1AA6h

BMC RX Low Level Half Bit Maximum Time Register (BMC_RX_LO_HB_MAX_TIME)

1AA7h

BMC RX Low Level Half Bit Minimum Time Register (BMC_RX_LO_HB_MIN_TIME)

1AA8h

BMC RX Squelch Assert Time Register (BMC_RX_SQL_ASSERT_TIME)

1AA9h

BMC RX Squelch Hold Time Register (BMC_RX_SQL_HOLD_TIME)

1AAAh – 1AAFh

Reserved for future expansion

1AB0h

BMC TX Bit-Time Count Register (BMC_TX_BITTIME_CNT)

1AB1h

BMC Transition Window Time Register (BMC_TRANSITION_WINDOW_TIME)

1AB2h – 1ABFh

Reserved for future expansion

1AC0h

BIST Control Register A (BIST_CTL_A)

1AC1h

BIST Control Register B (BIST_CTL_B)

1AC2h

BIST Error Count High Register (BIST_ERR_CNT_HI)

1AC3h

BIST Error Count Low Register (BIST_ERR_CNT_LO)

1AC4h – 1AC6h

Reserved for future expansion

1AC7h

BIST RX Status Register (BIST_RX_STAT)

1AC8h – 1BFFh

Reserved for future expansion

Note:

RESERVED address space must not be written under any circumstances. Failure to heed this warn-

ing may result in untoward operation and unexpected results.

TABLE 11-5:

POWER DELIVERY MAC REGISTER MAP (CONTINUED)

Address

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