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UPD360 датащи(PDF) 32 Page - Microchip Technology |
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UPD360 датащи(HTML) 32 Page - Microchip Technology |
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32 / 221 page ![]() UPD360 DS00002084C-page 32 2016-2017 Microchip Technology Inc. The UPD360 will be in ACTIVE_PPC_ON state when in USB Type-CTM Attached.SRC state with VBUS being driven by the internal 5V port power controller. 7.3 Asynchronous I2C Wakeup (UPD360-A/UPD360-B Only) The device supports asynchronous wakes on the I2C slave interface. Via clock stretching, the I2C transaction that caused the wakeup will not be lost and does not have to be repeated by the host. The device will not clock stretch for more than 3 us. The following steps illustrate the I2C wake function. Initially the Ring Oscillator and 48 MHz Oscillator are disabled. 1. The Host initiates an I2C transaction to the device. 2. The device asynchronously detects reception of the Start Bit and enables clock stretching by pulling-down I2C_- CLK after the host drives SCL low. The Ring Oscillator is asynchronously enabled and used as a clock source for the power management logic. 3. After a delay of approximately 5 us the oscillator stabilizes and clocks the I2C controller. 4. Clock stretching is disabled and the I2C controller is enabled and begins processing the pending transaction. 5. The I2C transaction completes. 6. The Host checks the device status to see if there are any pending transactions. The I2C transaction may have initiated a PD transmission or conversely a coincident PD transaction may be in the process of being received. 7. After host confirms the device has no pending transactions, it power downs the device by disabling the Ring Oscillator and 48 MHz Relaxation Oscillator via Clock Control Register (CLK_CTL). 8. The device is ready to accept future asynchronous I2C wake event. 7.4 Asynchronous SPI Wakeup (UPD360-C Only) UPD360 supports asynchronous wakes on the SPI interface. The SPI protocol for this device is defined such that there is no requirement that the SPI transaction must be repeated. The following steps illustrate the SPI wake function. Initially the Ring Oscillator and 48 MHz Oscillator are disabled. 1. The device is powered down. 2. The Host initiates an SPI transaction to the SPI Test Register (SPI_TEST) (UPD360-C Only) which, when the device is operational, returns a non-zero value. The device drives SPI_DO to 0b while in power-down. 3. The device detects reception of an SPI message. The Ring Oscillator is asynchronously enabled and used as a clock source for the power management logic. 4. After a delay of approximately 5 us the oscillator stabilizes and clocks the SPI controller. 5. The device processes the next received SPI transaction. 6. The SPI transaction(s) complete(s). 7. The Host checks the device status to see if there are any pending transactions. The SPI transaction may have initiated a PD transmission or conversely a coincident PD transaction may be in the process of being received. 8. After the Host confirms the device has no pending transactions, it powers down the device by disabling the Ring Oscillator, and 48 MHz Relaxation Oscillator via Clock Control Register (CLK_CTL). 9. The device drives SPI_DO to 0b and awaits an asynchronous SPI wake. |
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