UPD360 datasheet(123/221 Pages) MICROCHIP

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 2016-2017 Microchip Technology Inc.

DS00002084C-page 123

UPD360

11.2.1.2

RX FIFO Read Interface

Figure 11-3 shows how the read interface appears at various points of the software read.

The RX FIFO read interface always uses a FIFO access mode. The read is destructive, returning the current data and

releasing the FIFO space. Although the software may rewind the read pointer for test purposes, there is no guarantee

that the data has not been overwritten.

After determining the validity of data in the FIFO queue by reading the RX_FIFO_NOT_EMPTY bit in the RX Interrupt

Status Register (RX_IRQ_STAT), software may read the data from the RX FIFO. Software may read the entire packet

without the need to recheck the RX_FIFO_NOT_EMPTY bit.

Although written as each byte is received, valid data in the FIFO is only indicated once the entire packet is received and

validated.

Depending on the setting of the EN_SMBUS_MODE bit in the RX Control Register A (RX_CTL_A), either the status or

the Nbytes field is read first, followed by the other. If SMBus mode is enabled, the Nbytes field is read first and will

include the status byte, otherwise it is read second and just indicates the packet length. Note that the packet includes

the 4 byte CRC and the length includes this.

As the FIFO is accessed, packet data is read from the FIFO at the read pointer and following each read the read pointer

is incremented. The read pointer points to the next location to be read. Upon reaching the top of the RAM, the read

pointer wraps to 0.

The FIFO space is released as the packet is read. There is no need for software to specifically release the buffer space.

If software needs to flush a packet without reading the data, it may do so by writing the RX FIFO Read Pointer Register

(RX_FIFO_RD_PTR) and RX FIFO Read Pointer Control Bits Register (RX_FIFO_RD_PTR_CTL_BITS). Software

should add the appropriate value to the read pointer, taking into account the amount of data already read. Wrap at the

top of the RAM must be accounted, for both the read pointer and the RX_FIFO_RX_PTR_WRAP control bit. In order to

maintain coherency, the device will hold a write to the RX FIFO Read Pointer Register (RX_FIFO_RD_PTR) in a tem-

porary register and transfer it to the actual register when the RX FIFO Read Pointer Control Bits Register (RX_FI-

FO_RD_PTR_CTL_BITS) is written.

Although accessed as a FIFO, software can use any offset address in the 128 byte FIFO address range.

Although not recommended, the software can read from the FIFO if it is empty. The returned data will be 0 and the FIFO

will not underrun.

All pointers consist of a RAM address and a wrap indication. The wrap indication is toggled each time the pointer wraps

past the top of the RAM. The wrap indication is used in the full, “no room for header” and empty comparisons to distin-

guish between the write pointers being a full RAM size ahead of the read pointer (full conditions in which case the wrap

toggles would be opposite) and the write pointers being equal to the read pointer (empty condition in which case the

wrap toggles would be equal).

FIGURE 11-3:

READ INTERFACE VIEW OF RX FIFO

CRC (4)

byte m

byte 0

Message

Header

CRC (4)

byte n

byte 0

Message

Header

Ram Address

Nbytes*

Status*

1900h

197Fh

Free Space

<- Read Pointer

after packet reception

Nbytes*

Status*

CRC (4)

byte m

byte 0

Message

Header

CRC (4)

byte n

Ram Address

1900h

197Fh

Free Space

<- Read Pointer

during packet read

Nbytes*

Status*

CRC (4)

byte m

byte 0

Message

Header

*assuming SMBus mode = 0

Ram Address

1900h

197Fh

Free Space

<- Read Pointer

after 1

st packet read

Nbytes*

Status*

Ram Address

1900h

197Fh

Free Space

after 2

st packet read

<- Write Head Pointer,

Write Current Pointer

<- Write Head Pointer,

Write Current Pointer

<- Write Head Pointer,

Write Current Pointer,

Read Pointer

<- Write Head Pointer,

Write Current Pointer

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