UPD360 datasheet(22/221 Pages) MICROCHIP

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UPD360

DS00002084C-page 22

 2016-2017 Microchip Technology Inc.

5.2.2

MULTIPLE-BYTE REGISTER ADDRESS SEQUENCING

The DIR subfield in Address field bits [15:14] determines how multiple-byte sequences will be interpreted. This field is

held internally whenever issued with an address, but is not applied in I2C except in multiple-byte transfers, Read or

Write. The DIR field definitions are as follows:

• DIR = 00b: Selects auto-incrementing of the internally-held register address for subsequent byte accesses in a

multiple-byte packet.

• DIR = 10b: Selects auto-decrementing of the internally-held register address for subsequent byte accesses in a

multiple-byte packet.

• DIR = 11b: Select a fixed address. No modification of the internal register address will occur, meaning that all sub-

sequent accesses, single- or multiple-byte, are made to the same register.

• DIR = 01b: Reserved for future use.

Note that the DIR field is altered only by issuing an address. It remains, affecting any subsequent multiple-byte Read

packets, until altered.

5.2.3

GENERAL CALL ADDRESS

The device supports the I2C General Call Address. The intent of this feature is to enable global I2C writes to topologies

that have multiple UPD360 slaves. This minimizes the I2C transactions for device reset, via the Hardware Control Reg-

ister (HW_CTL), as well as for various common configuration registers. This mode of operation is intended for topologies

that consist solely of UPD360 slaves. This mode of operation may not be compatible with non-UPD360 slaves coexisting

on the I2C bus.

Only the case where the least significant bit, “B”, of the General Call address is set to one is supported. The device will

ignore the case when the least significant bit, “B”, of the General Call address is set to zero. For the latter case, the

device will ACK the first byte, General call address. The device will ignore and silently discard all subsequent bytes and

not acknowledge them. The second byte of the General Call address is also ignored and not acknowledged by the

device.

Figure 5-3 illustrates the supported General Call Address format.

5.2.4

DEVICE INITIALIZATION

Until the device has initialized itself to the point where the various configuration inputs are valid, the I2C slave interface

will not respond to or be affected by any external pin activity. The device should not be accessed by the master in this

state. If, however, it is necessary to do so, this state will appear externally as a NACK (high) in the ACK bit time of the

Control Byte, and of any further bytes transmitted by the master. The device will continue to act in this manner until the

first Start condition is received after it is initialized internally. A Read transaction should not be attempted until an

Address Write has been completed successfully (Figure 5-2), since the value(s) read may be unpredictable otherwise.

Alternatively, an IRQ_N pin assertion can be used to indicate the device is ready.

Note:

Within bytes (address and data), the bits are transferred most-significant bit first. Addresses are transferred

Most-Significant Byte first. All registers are accessed in units of bytes, and register data is transferred in

increasing byte address order. Refer to the device register layout to determine the effect of this on the sig-

nificance order of any multi-byte value.

FIGURE 5-3:

I2C GENERAL CALL ADDRESS

Address Byte 1

Start or

Stop or

Data

DIR

Address Byte 0

13 12 11 10

Inc /

Dec /

Static

Master Address

General Call

Address

(B)

Second Byte

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