XRT7250 datasheet(131/463 Pages) EXAR

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XRT7250

DS3/E3 FRAMER IC

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REV. 1.1.1

112

For a detailed description of the XRT7300 DS3/E3

LIU's operation, during each of these above-men-

tioned loop-back modes, please consult the XRT7300

DS3/E3/STS-1 LIU IC Data Sheet.

NOTE: If the customer is not using the XRT7300 DS3/E3/

STS-1 LIU IC, then this bit-field and the LLOOP output pin

can be used for other purposes.

2.3.8.20 Line Interface Scan Register

Bit 2 - DMO - (Drive Monitor Output)

This Read-Only bit-field indicates the logic state of

the DMO input pin of the Framer device. This input

pin is intended to be connected to the DMO output

pin of the XRT7300 DS3/E3 LIU IC. If this bit-field

contains a logic "1", then the DMO input pin is "High".

The XRT7300 DS3/E3 LIU IC will set this pin "High" if

the drive monitor circuitry (within the XRT7300 de-

vice) has not detected any bipolar signals at the MTIP

and MRING inputs (of the XRT7300 device) within the

last 128 + 32 bit periods.

Conversely, if this bit-field contains a logic "0", then

the DMO input pin is "High". The XRT7300 DS3/E3

LIU IC will set this pin "Low" if bipolar signals are be-

ing detected at the MTIP and MRING input pins.

NOTE: If this customer is not using the XRT7300 DS3/E3

LIU IC, then this input pin can be used for a variety of other

purposes.

Bit 1 - RLOL - (Receive Loss of Lock)

This Read-Only bit-field indicates the logic state of

the RLOL input pin of the Framer device. This input

pin is intended to be connected to the RLOL output

pin of the XRT7300 DS3/E3 LIU IC. If this bit-field

contains a logic "1", then the RLOL input pin is

"High". The XRT7300 DS3/E3 LIU IC will set this pin

"High" if the clock recovery phase-locked-loop circuit-

ry (within the XRT7300 device) has lost lock with the

incoming DS3/E3 data-stream and is not properly re-

covering clock and data.

Conversely, if this bit-field contains a logic "0", then

the RLOL input pin is "Low". The XRT7300 DS3/E3

LIU IC will hold this pin "Low" as long as this clock re-

covery phase-locked-loop circuitry (within the

XRT7300 device) is properly locked onto the incom-

ing DS3 data-stream, and is properly recovering clock

and data from this data-stream.

For more information on the operation of the

XRT7300 DS3/E3/STS-1 LIU IC, please consult the

XRT7300 DS3/E3/STS-1 LIU IC data sheet.

NOTE: If the customer is not using the XRT7300 DS3/E3/

STS-1 IC, then this bit-field, and the RLOL input pin can be

used for other purposes.

Bit 0 - RLOS - (Receive Loss of Signal)

This Read-Only bit-field indicates the logic state of

the RLOS input pin of the Framer device. This input

pin is intended to be connected to the RLOS output

pin of the XRT7300 DS3/E3 LIU IC. If this bit-field

contains a logic "1", then the RLOS input pin is

"High". The XRT7300 device will toggle this signal

"High" if it (the XRT7300 LIU IC) is currently declaring

an LOS (Loss of Signal) condition.

Conversely, if this bit-field contains a logic "0", then

the RLOS input pin is "Low". The XRT7300 device

will hold this signal "Low" if it is NOT currently declar-

ing an LOS (Loss of Signal) condition.

For more information on the LOS Declaration and

Clearance criteria of the XRT7300 device, please

consult the XRT7300 DS3/E3/STS-1 LIU IC data

sheet.

NOTE: Asserting the RLOS input pin will cause the

XRT7250 Framer IC device to generate the Change in LOS

Condition interrupt and declare an LOS (Loss of Signal)

condition. Therefore, this input pin should not be used as a

general purpose input.

2.4

THE LOSS OF CLOCK ENABLE FEATURE

The timing for the Microprocessor Interface section,

originates from a line rate (e.g., either a 34.368MHz

or 44.736 MHz) signal that is provided by either the

TxInClk or the RxLineClk signals. However, if the

Framer device experiences a Loss of Clock signal

event such that neither the TxInClk nor the RxLineClk

signal are present, then the Framer Microprocessor

Interface section cease to function.

The Framer device offers a Loss of Clock (LOC) pro-

tection feature that allows the Microprocessor Inter-

face section to at least complete or terminate an in-

process Read or Write cycle (with the local µP)

should this Loss of Clock event occur. The LOC cir-

cuitry consists of a ring oscillator that continuously

LINE INTERFACE SCAN REGISTER (ADDRESS = 0X81)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

DMO

RLOL

RLOS

000

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