XRT7250 datasheet(105/463 Pages) EXAR

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XRT7250

DS3/E3 FRAMER IC

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REV. 1.1.1

This Read-Only bit-field indicates whether or not the

FEAC Message Transmission Complete interrupt has

occurred since the last read of this register. This in-

terrupt will occur once the Transmit FEAC Processor

has finished its 10th transmission of the 16 bit FEAC

Message (6 bit FEAC Code word + 10 framing bits).

The purpose of this interrupt is to let the local µP

know that the Transmit FEAC Processor has complet-

ed its transmission of its latest FEAC Message and is

now ready to transmit another FEAC Message.

If this bit-field is "0", then the FEAC Message Trans-

mission Complete interrupt has NOT occurred since

the last read of this register.

If this bit-field is “1”, then the FEAC Message Trans-

mission Complete interrupt has occurred since the

last read of this register.

NOTE: For more information on the Transmit FEAC Proces-

sor, please see Section 3.2.3.1.

Bit 2 - TxFEAC Enable

This Read/Write bit-field allows the user to enable or

disable the Transmit FEAC Processor. The Transmit

FEAC Processor will NOT function until it has been

enabled.

Writing a "0" to this bit-field disables the Transmit

FEAC Processor. Writing a "1" to this bit-field en-

ables the Transmit FEAC Processor.

Bit 1 - TxFEAC Go

This bit-field allows the user to invoke the Transmit

FEAC Message command. Once this command has

been invoked, the Transmit FEAC Processor will do

the following:

• Encapsulate the 6 bit FEAC code word, from the Tx

DS3 FEAC Register (Address = 0x32) into a 16 bit

FEAC Message

• Serially transmit this 16-bit FEAC Message to the

far-end receiver via the outbound DS3 data-stream,

10 consecutive times.

NOTE: For more information on the Transmit FEAC Proces-

sor, please see Section 3.2.3.1.

Bit 0 - TxFEAC Busy

This Read-Only bit-field allows the local µP to poll

and determine if the Transmit FEAC Processor has

completed its 10th transmission of the 16-bit FEAC

Message. This bit-field will contain a "1", if the Trans-

mit FEAC Processor is still transmitting the FEAC

Message. This bit-field will toggle to "0", once the

Transmit FEAC Processor has completed its 10th

transmission of the FEAC Message.

NOTE: For more information on the Transmit FEAC Proces-

sor, please see Section 3.2.3.1.

2.3.5.3

Transmit DS3 FEAC Register (DS3

Applications)

This register contains a six (6) bit read/write field that

allows the user to write in the six-bit FEAC code word,

that is desired to be transmitted to the Far End Re-

ceive FEAC Processor, via the outgoing DS3 data

stream. The Transmit FEAC Processor will encapsu-

late this six-bit code into a 16-bit FEAC message, and

will proceed to transmit this message to the Remote

Receiver via the FEAC bit-field within each out-going

DS3 frame.

NOTE: For more information on the operation of the Trans-

mit FEAC Processor, please see Section 3.2.3.1.

2.3.5.4

Transmit DS3 LAPD Configuration

TXDS3 FEAC REGISTER (ADDRESS = 0X32)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

Not Used

TxFEAC[5:0]

Not Used

R/WR/W

111

110

TXDS3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

Not Used

Auto

Retransmit

Not Used

TxLAPD Msg

Length

TxLAPD

Enable

R/WR/W

001

000

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