DSP56857 datasheet(154/662 Pages) FREESCALE

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OSC (Oscillator) Circuit Detail

5685X Digital Signal Controller User Manual, Rev. 4

6-4

Freescale Semiconductor

oscillator’s Fref output. The core will run at Fref/2 and the IPBUS_CLK will run at Fref/4.

Among the first things applications typically do is turn on the PLL, wait for lock indication and

set CGMCR[SEL] to 1, enabling high speed operation.

6.1.1 OCCS Features

•

OSC connects to external crystals in the range of 2 to 4MHz

•

OSC can optionally accept an external active clock (0 to 240MHz)

•

PLL generates any integer multiple frequency, allowing DC to 120MHZ execution

•

CGM provides glitch-free transition between OSC and PLL clock sources

•

CGM provides digital loss of lock detection

•

Ultra Low Power modes are available while COP timer and TOD are kept alive

6.2 OSC (Oscillator) Circuit Detail

Figure 6-2. OSC Supplying Clocks to PLL/CGM

A typical connection for the OSC module is shown above. The weak differential signal coming in

directly from EXTAL/XTAL pin pair is routed to a very low power differential amplifier.

Because the amplifier is so low in power, it has a usable bandwidth limit somewhat above just

4MHz. The resulting clock frequency is divided down by a fixed value of 128 to yield a

31.25KHz clock. Out of reset, the register CGMCR[TOD_SEL] is 0, so this is the path selected

through the mux to create the TIME_CLK used by the COP and TOD. If the signal present on

XTAL is above 4MHz (e.g. driven by an external active clock) then it is necessary to set

CGMCR[TOD_SEL] to 1.

The signal from XTAL is buffered up (becoming Fref) and is consumed everywhere else.

Rbias

EXTAL

CGMCR[TOD_SEL]

“0” is default path

Note (1)

BOLD represents default states and typical

conditions.

1) See STOP Mode Features for further details

2) When OSC_LOPWR is asserted, this grayed

portion of the OCCS is disabled. OSC_LOPWR

assertion is prevented whenever CGMCR[TOD_SEL]

= 1. This automatic interlock prevents TIME_CLK from

being killed accidentally.

Fref

(4 MHz)

TIME_CLK (31.25 KHz)

XTAL

CGMTOD[TOD]

128

(1)

OSC_LOPWR

Notes (1) & (2)

Bandwidth limited

to 4 MHz

TIME_CLK feeds

the TOD and COP

watchdog timer.

4 MHz

CL1

CL2

Oscillator

PLL / CGM

Ftime

(31.25 KHz)

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