IMX7SCEC datasheet(14/152 Pages) NXP

14 / 152 page

Modules list

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

TZASC

Trust-Zone Address

Space Controller

Security

The TZASC (TZC-380 by ARM) provides security

address region control functions required for intended

application. It is used on the path to the DRAM

controller.

UART1

UART2

UART3

UART4

UART5

UART6

UART7

UART Interface

Connectivity

peripherals

Each of the UARTv2 modules support the following

serial data transmit/receive protocols and

configurations:

• 7- or 8-bit data words, 1 or 2 stop bits, programmable

parity (even, odd or none)

• Programmable baud rates up to 4 Mbps. This is a

higher max baud rate relative to the 1.875 MHz,

which is stated by the TIA/EIA-232-F standard.

• 32-byte FIFO on Tx and 32 half-word FIFO on Rx

supporting auto-baud

uSDHC1

uSDHC2

uSDHC3

SD/MMC and SDXC

Enhanced Multi-Media

Card / Secure Digital Host

Controller

Connectivity

peripherals

i.MX 7Solo SoC characteristics:

All the MMC/SD/SDIO controller IPs are based on the

uSDHC IP. They are designed to be:

• Fully compatible with MMC command/response sets

and Physical Layer as defined in the Multimedia

Card System Specification,

v5.0/v4.4/v4.41/v4.4/v4.3/v4.2.

• Fully compatible with SD command/response sets

and Physical Layer as defined in the SD Memory

Card Specifications v 3.0 including high-capacity

SDXC cards up to 2 TB.

• Fully compatible with SDIO command/response sets

and interrupt/Read-Wait mode as defined in the

SDIO Card Specification, Part E1, v. 3.0

All the ports support:

• 1-bit or 4-bit transfer mode specifications for SD and

SDIO cards up to UHS-I SDR104 mode (104 MB/s

max)

• 1-bit, 4-bit, or 8-bit transfer mode specifications for

MMC cards up to 200 MHz in both SDR and DDR

modes, including HS200 and HS400.

However, the SoC level integration and I/O muxing logic

restrict the functionality to the following:

• uSDHC1 and uSDHC2 are primarily intended to

serve as external slots or interfaces to on-board

SDIO devices. These ports are equipped with “Card

detection” and “Write Protection” pads and do not

support hardware reset.

• uSDHC3 is primarily intended to serve interfaces to

embedded MMC memory or interfaces to on-board

SDIO devices. These ports do not have “Card

detection” and “Write Protection” pads and do

support hardware reset.

• All ports can work with 1.8 V and 3.3 V cards. There

are two completely independent I/O power domains

for uSDHC1 and uSDHC2 in 4-bit configuration (SD

interface). uSDHC3 is placed in his own independent

power domain.

Table 2. i.MX 7Solo modules list(continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

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