IMX7SCEC datasheet(47/152 Pages) NXP

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Electrical characteristics

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

Table 33 shows DDR I/O output buffer impedance of i.MX 7Solo family of processors.

Note:

1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.

2. Calibration is done against 240

Ω external reference resistor.

3. Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.

4.7.2

Differential I/O output buffer impedance

The Differential CCM interface is designed to be compatible with TIA/EIA 644-A standard. See, TIA/EIA

STANDARD 644-A, Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface

Circuits (2001) for details.

4.7.3

USB battery charger detection driver impedance

The USB_OTG1_CHD_B open-drain output pin can be used to signal the results of USB Battery Charger

detection routines for the USB_OTG1 PHY instance to power management and monitoring devices. Use

of this pin requires an external pullup resistor, for more information see Table 3, and Table 7.

Table 34 shows the USB_OTG1_CHD_B pulldown driver impedance for the USB_OTG1_CHD_B pin.

4.8

System modules timing

This section contains the timing and electrical parameters for the modules in each i.MX 7Solo processor.

Table 33. DDR I/O output buffer impedance

Parameter

Symbol

Test Conditions DSE

(Drive Strength)

Typical

Unit

NVCC_DRAM=1.5 V

(DDR3)

DDR_SEL=11

NVCC_DRAM=1.2 V

(LPDDR2)

DDR_SEL=10

Output Driver

Impedance

Rdrv

000

001

010

011

100

101

110

111

Hi-Z

240

120

Hi-Z

240

120

Table 34. USB_OTG1_CHD_B pulldown driver impedance (VDD_USB_OTG1_3P3_IN 3.3 V)

Parameter

Symbol

Typical

Unit

Open-drain output driver pulldown impedance

Rdrv_pd

1000

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