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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX7SCEC датащи(PDF) 85 Page - NXP Semiconductors |
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IMX7SCEC датащи(HTML) 85 Page - NXP Semiconductors |
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85 / 152 page  Electrical characteristics i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017 NXP Semiconductors 85 4.10.3.1.3 MII asynchronous inputs signal timing (ENET_CRS and ENET_COL) Figure 53 shows MII asynchronous input timings. Table 61 describes the timing parameter (M9) shown in the figure. Figure 53. MII async inputs timing diagram 1 ENET_COL has the same timing in 10-Mbit 7-wire interface mode. 4.10.3.1.4 MII Serial management channel timing (ENET_MDIO and ENET_MDC) The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3 MII specification. However the ENET can function correctly with a maximum MDC frequency of 15 MHz. Figure 54 shows MII asynchronous input timings. Table 62 describes the timing parameters (M10–M15) shown in the figure. Figure 54. MII serial management channel timing diagram Table 61. MII asynchronous inputs signal timing ID Characteristic Min. Max. Unit M91 ENET_CRS to ENET_COL minimum pulse width 1.5 — ENET_TX_CLK period ENET_CRS, ENET_COL M9 ENET_MDC (output) ENET_MDIO (output) M14 M15 M10 M11 M12 M13 ENET_MDIO (input) |
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