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IMX7SCEC датащи(PDF) 93 Page - NXP Semiconductors |
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IMX7SCEC датащи(HTML) 93 Page - NXP Semiconductors |
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93 / 152 page ![]() Electrical characteristics i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017 NXP Semiconductors 93 The following subsections describe the CSI timing in gated and ungated clock modes. 4.10.8 MIPI PHY timing parameters 4.10.8.1 This section describes MIPI PHY electrical specifications Electrical and Timing Information Table 69. Electrical and Timing Information Symbol Parameters Test Conditions Min Typ Max Unit Input DC Specifications - Apply to DSI_CLK_P/DSI_CLK_N and DSI_DATA_P/DSI_DATA_N inputs VI Input signal voltage range Transient voltage range is limited from -300 mV to 1600 mV -50 — 1350 mV VLEAK Input leakage current VGNDSH(min) = VI = VGNDSH(max) + VOH(absmax) Lane module in LP Receive Mode -10 — 10 mA VGNDSH Ground Shift — -50 — 50 mV VOH(absmax) Maximum transient output voltage level —— — 1.45 V tvoh(absmax) Maximum transient time above VOH(absmax) —— — 20 ns HS Line Drivers DC Specifications |VOD| HS Transmit Differential output voltage magnitude 80 Ω<= RL< = 125 Ω 140 200 270 mV Δ|VOD| Change in Differential output voltage magnitude between logic states 80 Ω<= RL< = 125 Ω —— 10 mV VCMTX Steady-state common-mode output voltage. 80 Ω<= RL< = 125 Ω 150 200 250 mV ΔVCMTX(1,0) Changes in steady-state common-mode output voltage between logic states 80 Ω<= RL< = 125 Ω —— 5 mV VOHHS HS output high voltage 80 Ω<= RL< = 125 Ω — — 360 mV ZOS Single-ended output impedance. —40 50 62.5 Ω ΔZOS Single-ended output impedance mismatch. —— — 10 % LP Line Drivers DC Specifications VOL Output low-level SE voltage — -50 50 mV VOH Output high-level SE voltage — 1.1 1.2 1.3 V |
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