IMX7SCEC datasheet(32/152 Pages) NXP

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Electrical characteristics

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

4.1.8

Power-up sequence

The i.MX7 processor has the following power-up sequence requirements:

•

VDD_SNVS_IN to be turned on before any other power supply. If a coin cell is used to power

VDD_SNVS_IN, then ensure that it is connected before any other supply is switched on.

•

VDD_SOC to be turned on before NVCC_DRAM and NVCC_DRAM_CKE.

•

VDD_ARM, VDD_SOC, VDDA_1P8_IN, VDD_LPSR_IN and all I/O power (NVCC_*) should

be turned on after VDD_SVNS_IN is active. But there is no sequence requirement among these

power rails other than the sequence requirement between VDD_SOC and

NVCC_DRAM/NVCC_DRAM_CKE.

•

There are no special timing requirements for VDD_USB_OTG1_3P3_IN and

VDD_USB_OTG2_3P3_IN.

The POR_B input (if used) must be immediately asserted at power-up and remain asserted until the last

power rail reaches its working voltage. In the absence of an external reset feeding the POR_B input, the

internal POR module takes control.

The power-up sequence is shown in Figure 4 with the following timing parameters:

Time from SVNS power stable to other power rails start to ramp, minimal delay is 2ms,

no max delay requirement.

Time from first power rails (except SNVS) ramp up to all the power rails get stable,

minimal delay is 0ms, no max delay requirement.

Time from all power rails get stable to power-on reset, minimal delay is 0ms, no max

delay requirement.

Time from VDD_SOC get stable to NVCC_DRAM/NVCC_DRAM_CKE start to

ramp, minimal delay is 0ms, no max delay requirement.

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