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Electrical characteristics

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

4.7

Output buffer impedance parameters

This section defines the I/O impedance parameters of the i.MX 7Solo family of processors for the

following I/O types:

•

Double Data Rate I/O (DDR) for LPDDR2, LPDDR3, and DDR3/DDR3L modes

•

Differential I/O (CCM_CLK1)

•

USB battery charger detection open-drain output (USB_OTG1_CHD_B)

NOTE

DDR I/O output driver impedance is measured with “long” transmission

line of impedance Ztl attached to I/O pad and incident wave launched into

transmission line. Rpu/Rpd and Ztl form a voltage divider that defines

specific voltage of incident wave relative to OVDD. Output driver

impedance is calculated from this voltage divider (see Figure 9).

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