IMX7SCEC datasheet(48/152 Pages) NXP

номер детали	IMX7SCEC

подробное описание детали	i.MX 7Solo Family

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Electrical characteristics

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

4.8.1

Reset timings parameters

Figure 10 shows the reset timing and Table 35 lists the timing parameters.

Figure 10. Reset timing diagram

4.8.2

WDOG Reset timing parameters

Figure 11 shows the WDOG reset timing and Table 36 lists the timing parameters.

Figure 11. WDOG

x_B timing diagram

NOTE

RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or

approximately 30

μs.

NOTE

WDOGx_B output signals (for each one of the Watchdog modules) do not

have dedicated pins, but are muxed out through the IOMUX. See the

IOMUXC chapter of the i.MX 7Solo Application Processor Reference Manual

(IMX7SRM) for detailed information.

4.8.3

External interface module (EIM)

The following subsections provide information on the EIM.

Table 35. Reset timing parameters

Parameter

Min

Max

Unit

CC1

Duration of POR_B to be qualified as valid.

Note: POR_B rise/fall times must be 5 ns or less.

1—

RTC_XTALI cycle

Table 36. WDOG

x_B timing parameters

Parameter

Min

Max

Unit

CC3

Duration of WDOG1_B Assertion

—

RTC_XTALI cycle

POR_B

CC1

(Input)

WDOG

x_B

CC3

(Output)

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