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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX7SCEC датащи(PDF) 65 Page - NXP Semiconductors |
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IMX7SCEC датащи(HTML) 65 Page - NXP Semiconductors |
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65 / 152 page  Electrical characteristics i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017 NXP Semiconductors 65 4.8.4.3 LPDDR2 parameters Figure 30 shows the LPDDR2 basic timing diagram. The timing parameters for this diagram appear in Table 46. Figure 30. LPDDR2 command and address timing diagram Table 46. LPDDR2 timing parameters1,2 1 All measurements are in reference to Vref level. 2 Measurements were done using balanced load and 25 Ω resistor from outputs to DDR_VREF ID Parameter Symbol CK = 533 MHz Unit Min Max LP1 SDRAM clock high-level width tCH 0.45 0.55 tCK LP2 SDRAM clock low-level width tCL 0.45 0.55 tCK LP3 DRAM_CSx_B, DRAM_SDCKEx setup time tIS 370 — ps LP4 DRAM_CSx_B, DRAM_SDCKEx hold time tIH 370 — ps LP3 DRAM_CAS_B setup time tIS 770 — ps LP4 DRAM_CAS_B hold time tIH 770 — ps DRAM_SDCLKx_P DRAM_CSx_B DRAM_SDCKEx DRAM_CAS_B LP4 LP4 LP3 LP4 LP3 LP2 LP3 LP3 LP1 |
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