IMX7SCEC datasheet(86/152 Pages) NXP

номер детали	IMX7SCEC

подробное описание детали	i.MX 7Solo Family

PDF	152 Pages

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Electrical characteristics

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

4.10.3.2

RMII mode timing

In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference

clock. ENET_RX_EN is used as the ENET_RX_EN in RMII. Other signals under RMII mode include

ENET_TX_EN, ENET_TX_DATA[1:0], ENET_RX_DATA[1:0] and ENET_RX_ER.

Figure 55 shows RMII mode timings. Table 63 describes the timing parameters (M16–M21) shown in the

figure.

Figure 55. RMII mode signal timing diagram

Table 62. MII serial management channel timing

Characteristic

Min.

Max.

Unit

M10

ENET_MDC falling edge to ENET_MDIO output invalid (min.

propagation delay)

0—

M11

ENET_MDC falling edge to ENET_MDIO output valid (max.

propagation delay)

—5

M12

ENET_MDIO (input) to ENET_MDC rising edge setup

—

M13

ENET_MDIO (input) to ENET_MDC rising edge hold

—

M14

ENET_MDC pulse width high

40%

60%

ENET_MDC period

M15

ENET_MDC pulse width low

40%

60%

ENET_MDC period

ENET_CLK (input)

ENET_TX_EN

M16

M17

M18

M19

M20

M21

ENET_RX_DATA[1:0]

ENET_TX_DATA (output)

ENET_RX_ER

ENET_RX_EN (input)

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