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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX7SCEC датащи(PDF) 81 Page - NXP Semiconductors |
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IMX7SCEC датащи(HTML) 81 Page - NXP Semiconductors |
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81 / 152 page  Electrical characteristics i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017 NXP Semiconductors 81 4.10.2.4 HS200 Mode Timing Figure 49 depicts the timing of HS200 mode, and Table 57 lists the HS200 timing characteristics. Figure 49. HS200 Mode Timing uSDHC input/Card Outputs DAT (Reference to Strobe) SD6 uSDHC input skew tRQ — 0.45 ns SD7 uSDHC hold skew tRQH — 0.45 ns Table 57. HS200 Interface Timing Specification ID Parameter Symbols Min Max Unit Card Input Clock SD1 Clock Frequency Period tCLK 5.0 — ns SD2 Clock Low Time tCL 0.3*tCLK 0.7*tCLK ns SD2 Clock High Time tCH 0.3*tCLK 0.7*tCLK ns uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK) SD5 uSDHC Output Delay tOD –1.6 1 ns uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1 1HS200 is for 8 bits while SDR104 is for 4 bits. SD8 Card Output Data Window tODW 0.5*tCLK —ns Table 56. HS400 interface timing specifications(continued) ID Parameter Symbols Min Max Unit |
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