IMX7SCEC datasheet(92/152 Pages) NXP

92 / 152 page

Electrical characteristics

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

4.10.7.2

Ungated clock mode timing

Figure 63 shows the ungated clock mode timings of CSI, and Table 68 describes the timing parameters

(P1–P6) that are shown in the figure. In ungated mode the CSI_VSYNC and CSI_PIXCLK signals are

used, and the CSI_HSYNC signal is ignored.

Figure 63. CSI Ungated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge

The CSI enables the chip to connect directly to external CMOS image sensors, which are classified as

dumb or smart as follows:

•

Dumb sensors only support traditional sensor timing (vertical sync (VSYNC) and horizontal sync

(HSYNC)) and output-only Bayer and statistics data.

•

Smart sensors support CCIR656 video decoder formats and perform additional processing of the

image (for example, image compression, image pre-filtering, and various data output formats).

CSI DATA hold time

tDh

—

CSI pixel clock high time

tCLKh

3.75

—

CSI pixel clock low time

tCLKl

3.75

—

CSI pixel clock frequency

fCLK

—

148.5

MHz

Table 68. CSI Ungated Clock Mode Timing Parameters

Parameter

Symbol

Min.

Max.

Units

CSI_VSYNC to pixel clock time

tVSYNC

33.5

—

CSI DATA setup time

tDsu

—

CSI DATA hold time

tDh

—

CSI pixel clock high time

tCLKh

3.75

—

CSI pixel clock low time

tCLKl

3.75

—

CSI pixel clock frequency

fCLK

—

148.5

MHz

Table 67. CSI Gated Clock Mode Timing Parameters(continued)

Parameter

Symbol

Min.

Max.

Units

CSI_PIXCLK

CSI_VSYNC

CSI_DATA[15:00]

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