LAN9220 datasheet(11/142 Pages) MICROCHIP

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DS00002417A-page 11

LAN9220

TABLE 2-4:

SYSTEM AND POWER SIGNALS

Name

Symbol

Buffer

Type

# Pins

Description

Crystal 1, Clock In

XTAL1/CLKIN

lCLK

External 25MHz Crystal Input. This pin can also

be connected to single-ended TTL oscillator

(CLKIN). If this method is implemented, XTAL2

should be left unconnected.

Crystal 2

XTAL2

OCLK

External 25MHz Crystal output.

Reset

nRESET

VIS

(PU)

Active-low reset input. Resets all logic and

registers within the LAN9220. This signal is

pulled high with a weak internal pull-up resistor.

Note:

The LAN9220 must be reset on

power-up via nRESET or following

power-up via a soft reset (SRST).

The LAN9220 must always be read

at least once after reset, or upon

return from a power-saving state or

write operations will not function.

See Section 3.11, "Detailed Reset

Description," on page 39 for addi-

tional information

Note:

When

operating

reduced

VDDVARIO voltage levels (less than

3.0V), this pin must be pulled-high to

a valid level with an external resistor

or must be driven as an input. Refer

Section

2.2,

"External

Pull-

Up/Pull-Down Resistors" for more

information.

Wakeup Indicator

PME

VO8/

VOD8

When programmed to do so, is asserted when

the LAN9220 detects a wake event and is

requesting the system to wake up from the

associated sleep state. The polarity and buffer

type of this signal is programmable.

Note:

Detection of a Power Management

Event, and assertion of the PME sig-

nal will not wakeup the LAN9220.

The LAN9220 will only wake up

when it detects a host write cycle

(assertion

nCS

and

nWR).

Although any write to the LAN9220,

regardless of the data written, will

wake-up the device when it is in a

power-saving mode, it is required

that the BYTE_TEST register be

used for this purpose.

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