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LAN9220 датащи(PDF) 70 Page - Microchip Technology

номер детали LAN9220
подробное описание детали  16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
PDF  142 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9220 датащи(HTML) 70 Page - Microchip Technology

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LAN9220
DS00002417A-page 70
 2006-2017 Microchip Technology Inc.
5.3.3
INT_STS—INTERRUPT STATUS REGISTER
This register contains the current status of the generated interrupts. Writing a 1 to the corresponding bits acknowledges
and clears the interrupt.
4
IRQ Polarity (IRQ_POL) – When cleared, enables the IRQ line to
function as an active low output. When set, the IRQ output is active high.
When IRQ is configured as an open-drain output this field is ignored,
and the interrupt output is always active low.
R/W
NASR
0
3-1
Reserved
RO
-
0
IRQ Buffer Type (IRQ_TYPE) – When cleared, enables IRQ to function
as an open-drain buffer for use in a Wired-Or Interrupt configuration.
When set, the IRQ output is a Push-Pull driver. When configured as an
open-drain output the IRQ_POL field is ignored, and the interrupt output
is always active low.
R/W
NASR
0
Offset:
58h
Size:
32 bits
Bits
Description
Type
Default
31
Software Interrupt (SW_INT). This interrupt is generated when the
SW_INT_EN bit is set high. Writing a one clears this interrupt.
R/WC
0
30-26
Reserved
RO
-
25
TX Stopped (TXSTOP_INT). This interrupt is issued when STOP_TX bit
in TX_CFG is set, and the transmitter is halted.
R/WC
0
24
RX Stopped (RXSTOP_INT). This interrupt is issued when the receiver is
halted.
R/WC
0
23
RX Dropped Frame Counter Halfway (RXDFH_INT). This interrupt is
issued when the RX Dropped Frames Counter counts past its halfway
point (7FFFFFFFh to 80000000h).
R/WC
0
22
Reserved
RO
0
21
TX IOC Interrupt (TX_IOC). When a buffer with the IOC flag set has
finished being loaded into the TX FIFO, this interrupt is generated.
R/WC
0
20
RX DMA Interrupt (RXD_INT). This interrupt is issued when the amount
of data programmed in the RX DMA Count (RX_DMA_CNT) field of the
RX_CFG register has been transferred out of the RX FIFO.
R/WC
0
19
GP Timer (GPT_INT). This interrupt is issued when the General Purpose
timer wraps past zero to FFFFh.
R/WC
0
18
PHY (PHY_INT). Indicates a PHY Interrupt event.
RO
0
Bits
Description
Type
Default



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