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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LAN9220 датащи(PDF) 79 Page - Microchip Technology |
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LAN9220 датащи(HTML) 79 Page - Microchip Technology |
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79 / 142 page  2006-2017 Microchip Technology Inc. DS00002417A-page 79 LAN9220 5.3.11 RX_FIFO_INF—RECEIVE FIFO INFORMATION REGISTER This register contains the used space in the receive FIFOs of the LAN9220 Ethernet Controller. 5.3.12 TX_FIFO_INF—TRANSMIT FIFO INFORMATION REGISTER This register contains the free space in the transmit data FIFO and the used space in the transmit status FIFO in the LAN9220. Offset: 7Ch Size: 32 bits Bits Description Type Default 31-24 Reserved RO - 23-16 RX Status FIFO Used Space (RXSUSED). Indicates the amount of space in DWORDs, used in the RX Status FIFO. RO 00h 15-0 RX Data FIFO Used Space (RXDUSED).). Reads the amount of space in bytes, used in the RX data FIFO. For each receive frame, this field is incremented by the length of the receive data rounded up to the nearest DWORD (if the payload does not end on a DWORD boundary). RO 0000h Offset: 80h Size: 32 bits Bits Description Type Default 31-24 Reserved RO - 23-16 TX Status FIFO Used Space (TXSUSED). Indicates the amount of space in DWORDS used in the TX Status FIFO. RO 00h 15-0 TX Data FIFO Free Space (TDFREE). Reads the amount of space in bytes, available in the TX data FIFO. The application should never write more data than is available, as indicated by this value. RO 1200h |
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