LAN9220 datasheet(38/142 Pages) MICROCHIP

38 / 142 page

LAN9220

DS00002417A-page 38

 2006-2017 Microchip Technology Inc.

3.10.3

INTERNAL PHY POWER-DOWN MODES

There are 2 power-down modes for the internal PHY:

3.10.3.1

General Power-Down

This power-down is controlled by register 0, bit 11. In this mode the internal PHY, except the management interface, is

powered-down and stays in that condition as long as Phy register bit 0.11 is HIGH. When bit 0.11 is cleared, the PHY

powers up and is automatically reset. Please refer to Section 5.5.1, "Basic Control Register," on page 105 for additional

information on this register.

3.10.3.2

Energy Detect Power-Down

This power-down mode is activated by setting the Phy register bit 17.13 to 1. Please refer to Section 5.5.8, "Mode Con-

trol/Status," on page 109 for additional information on this register. In this mode when no energy is present on the line,

the PHY is powered down, with the exception of the management interface, the SQUELCH circuit and the ENERGYON

logic. The ENERGYON logic is used to detect the presence of valid energy from 100Base-TX, 10Base-T, or Auto-nego-

tiation signals

In this mode, when the ENERGYON signal is low, the PHY is powered-down, and nothing is transmitted. When energy

is received - link pulses or packets - the ENERGYON signal goes high, and the PHY powers-up. It automatically resets

itself into the state it had prior to power-down, and asserts the INT7.1 bit of the register defined in Section 5.5.11, "Inter-

rupt Source Flag," on page 112. If the ENERGYON interrupt is enabled, this event will cause an interrupt to the host.

The first and possibly the second packet to activate ENERGYON may be lost. When 17.13 is low, energy detect power-

down is disabled.

FIGURE 3-18:

PME AND PME_INT SIGNAL GENERATION

PME

ED_EN

WOL _EN

50ms

PME_EN

PME_IND

PME_POL

PME_TYPE

LOGIC

WUEN

MPEN

phy_int

WUPS

WUFR

MPR

Denotes a level‐triggered "sticky" status bit

PME_INT_EN

PME_INT

IRQ_EN

IRQ

Other System

Interrupts

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